SEMICONDUCTOR DEVICE WITH INTEGRATED COILS

• US 20080290992A1
• Filed: 05/25/2007
• Published: 11/27/2008
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Knott, Bernhard, Hoeglauer, Josef
• Granted Patent: US 8,169,285 B2
• Time in Patent Office: Days
• US Class Current: 340/10.1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor device with a number of integrated coils is disclosed. In one embodiment, a first coil portion and a second coil portion are at least in part overlapping each other. Another embodiment provides a process for manufacturing a semiconductor device having at least the processes of generating a first coil portion, generating a second coil portion, wherein at least a part of the first coil portion and a part of the second coil portion are overlapping each other.

Claims

1. A semiconductor device comprising:

a number of integrated coils, wherein a first coil portion and a second coil portion are at least in part overlapping each other.

2. The semiconductor device of claim 1, comprising where the first coil portion and the second coil portion are part of one integrated coil.

3. The semiconductor device of claim 1, comprising where the first coil portion and the second coil portion belong to different integrated coils of the semiconductor device.

4. The semiconductor device of claim 1, comprising wherein the first coil portion and the second coil portion are positioned at least in part in different layers of the semiconductor device.

5. The semiconductor device of claim 1, comprising wherein at least a part of the first coil portion is arranged in a first layer and at least a part of the second coil portion is arranged in a second layer, wherein the first and second layer are substantially parallel aligned and in a vertical arrangement to each other.

6. The semiconductor device of claim 1, comprising wherein at least a part of the first coil portion is arranged on a chip of the semiconductor device and at least a part of the second coil portion is arranged on a chip carrier or substrate of the semiconductor device.

7. The semiconductor device of claim 1, comprising wherein a number of conductor paths of the integrated coil are extending at least in part across a chip of the semiconductor device.

8. The semiconductor device of claim 1, comprising wherein a number of conductor lines of the integrated coil are extending at least in part across a chip carrier or substrate of the semiconductor device.

9. The semiconductor device of claim 1, comprising wherein the first coil portion and the second coil portion provide a coil pair.

10. The semiconductor device of claim 1, comprising wherein the first coil portion provide a lower portion of an integrated coil and the second coil portion provide an upper portion of an integrated coil or the first coil portion provide an upper portion of an integrated coil and the second coil portion provide a lower portion of an integrated coil.

11. The semiconductor device of claim 1, comprising wherein a number of windings or conductor lines of the integrated coil are realized by using wire bonds.

12. The semiconductor device of claim 1, comprising wherein a number of conductor lines of the integrated coil are printed conductor paths made of conductive material.

13. The semiconductor device of claim 1, comprising wherein a number of conductor lines of the integrated coil are generated by using an conductive fluid, carbon ink, silver ink or copper ink.

14. The semiconductor device of claim 1, comprising wherein a number of conductor lines of the integrated coil are arranged on a chip of the semiconductor device.

15. The semiconductor device of claim 1, comprising wherein a number of conductor lines of the integrated coil are arranged on a chip carrier or substrate of the semiconductor device.

16. The semiconductor device of claim 1, comprising wherein a number of windings of the integrated coil are isolated conductor paths.

17. The semiconductor device of claim 1, comprising wherein a number of windings of the integrated coil are structured a conductor path generated by respective manufacturing processes producing a respective structure.

18. The semiconductor device of claim 1, comprising wherein a number of windings of the integrated coil are structured as an isolated printed conductor path made of conductive material, as a structured lead frame, and/or as an adhesive foil.

19. The semiconductor device of claim 1, comprising wherein the adhesive foil is pre-structured and arranged on a chip and/or on a chip carrier or substrate of the semiconductor device.

20. The semiconductor device of claim 1, comprising wherein the first coil portion and the second coil portion provide coil pairs arranged as two separate coil pairs, or as a bifilar coil.

21. The semiconductor device of claim 1, further comprising electrodes or pads for contacting the first and/or second coil portion.

22. The semiconductor device of claim 1, comprising wherein the electrodes or pads are contacted by bonding wires, and the bonding wires provide at least a part of the first and/or second coil portion.

23. A method for manufacturing a semiconductor device comprising:

generating a first coil portion;

generating a second coil portion;

wherein at least a part of the first coil portion and a part of the second coil portion are overlapping each other.

24. The method of claim 23, comprising generating the first coil portion and the second coil portion in such manner that the first coil portion and the second coil portion are positioned at least in part in different layers of the semiconductor device.

25. The method of claim 23, comprising generating the first coil portion and the second coil portion in a manner that at least a part of the first coil portion is arranged in a first layer and at least a part of the second coil portion is arranged in a second layer, wherein the first and second layer are substantially parallel aligned and in a vertical arrangement to each other.

26. The method of claim 23, comprising generating the first coil portion and the second coil portion in a manner that at least a part of a coil portion is arranged on a chip of the semiconductor device and at least a part of a coil portion is arranged on a chip carrier or substrate of the semiconductor device.

27. The method of claim 23, comprising generating the coil portions on the front and/or on the rear side of the chip carrier or substrate of the semiconductor device.

28. The method of claim 23, generating a connection between conductive lines on the front and rear sides of the chip carrier or substrate by trench etching and subsequent filling of the trenches with conductive material.

29. The method of claim 23, comprising printing the coil portions onto a chip and/or onto a chip carrier or substrate of the semiconductor device.

30. The method of claim 23, comprising generating the coil portions by using metallization deposition on a chip and/or on a chip carrier or substrate of the semiconductor device.

31. The method of claim 23, comprising generating the first coil portion and/or the second coil portion after mounting of one or more chips onto the chip carrier or substrate of the semiconductor device.

32. The method of claim 23, comprising performing the mounting of one or more chips onto the substrate or chip carrier of the semiconductor device by using an adhesive material.

33. The method of claim 23, comprising mounting of one or more chips onto the substrate or chip carrier of the semiconductor device is performed by forming chamfers made of adhesive material or glue on sidewalls of the chip.

34. The method of claim 23, comprising forming conductive paths or lines across the chamfers on sidewalls of the chip.

35. The method of claim 23, comprising fabricating a number of semiconductor devices in parallel on a common substrate.

36. The method of claim 23, comprising separating semiconductor devices fabricated in parallel on a common substrate by dicing, cutting or sawing the common substrate in parts.

40. A system comprising:

a semiconductor device manufactured by a method of claim 23.

37. A system comprising:

a semiconductor device having a number of integrated coils, wherein a first coil portion and a second coil portion are at least in part overlapping each other; and

an integrated circuit coupled to the semiconductor device.

38. The system of claim 37, comprising:

where the system further comprises an RFID chip.

39. The system of claim 37, comprising:

an external device, configured to communicate with the semiconductor device via at least one of the number of integrated coils.