Sub-array architecture memory devices and related systems and methods

• US 20080291760A1
• Filed: 05/23/2007
• Published: 11/27/2008
• Est. Priority Date: 05/23/2007
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nakanishi, Takuya, Ito, Koichiro
• Application Number:
  US11/805,750
• Publication Number:
  US 20080291760A1
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 29/80 with improved layout
• CPC Class Codes: G11C 29/84 with improved access time or stability
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

Memory devices, systems and methods implementing an architecture for partitioning a memory area of normally used memory cells and redundant memory cells are disclosed. A memory area is partitioned into a plurality of substantially equally sized sub-arrays of normally used memory cells and redundant memory cells. The groups of memory cells in a first portion of the sub-arrays are each selectable by a first quantity of select signals and a second portion of the sub-arrays are each selectable by a second quantity of select signals. One of the plurality of sub-arrays partially includes all of the groups of the redundant memory cells selectable by respective redundant select signals.

Claims

1. A method for partitioning a memory area, comprising:

aggregating selectable groups of normally used memory cells and redundant memory cells; and

partitioning a substantially equal quantity of the selectable groups into each of a plurality of sub-arrays with each of the selectable groups of the redundant memory cells being allocated to one of the plurality of sub-arrays.

2. The method of claim 1, further comprising structuring the selectable groups of the normally used memory cells to be individually selectable based on column select (CS) signals.

3. The method of claim 1, further comprising structuring the selectable groups of the redundant memory cells to be individually selectable based on redundant column select (RCS) signals.

4. The method of claim 1, wherein partitioning comprises partitioning an equal quantity of the selectable groups into each of a plurality of sub-arrays with each of the selectable groups of the redundant memory cells being allocated to one of the plurality of sub-arrays.

5. The method of claim 1, wherein partitioning comprises partitioning a first portion of the plurality of sub-arrays to include a first quantity of selectable groups and a second portion of the plurality of sub-arrays to include a second quantity of selectable groups differing from the first quantity of selectable groups by one.

6. The method of claim 1, further comprising bussing together inputs/outputs of each of the selectable groups of the normally used memory cells.

7. The method of claim 1, further comprising bussing together inputs/outputs of each of the selectable groups of the redundant memory cells.

8. A method for forming a memory area including a plurality of sub-arrays, the method comprising:

forming a plurality of normally used memory cell sub-arrays each including a substantially equal quantity of selectable groups of normally used memory cells; and

forming another sub-array including a quantity of selectable groups of normally used memory cells and all of the selectable groups of redundant memory cells, wherein each of the plurality of normally used memory cell sub-arrays and the another sub-array include substantially equal quantities of selectable groups.

9. The method of claim 8, further comprising:

generating column select (CS) signals for selecting the selectable groups of the normally used memory cells; and

generating redundant column select (RCS) signals for selecting the selectable groups of the redundant memory cells.

10. The method of claim 8, further comprising configuring each of the plurality of normally used memory cell sub-arrays and the another sub-array to each include an equal quantity of selectable groups.

11. The method of claim 8, further comprising configuring each of the plurality of normally used memory cell sub-arrays to include a quantity of selectable groups and the another sub-array to include a quantity of selectable groups differing from the quantity of selectable groups of the plurality of normally used sub-arrays by only one selectable group.

12. The method of claim 8, further comprising bussing together inputs/outputs of each of the selectable groups of the normally used memory cells.

13. The method of claim 8, further comprising bussing together inputs/outputs of each of the selectable groups of the redundant memory cells.

14. A memory device, comprising:

a plurality of normally used memory cell sub-arrays each including a substantially equal quantity of selectable groups of normally used memory cells; and

another sub-array including a quantity of selectable groups of normally used memory cells and all of the selectable groups of redundant memory cells, wherein each of the plurality of normally used memory cell sub-arrays and the another sub-array include substantially equal quantities of selectable groups.

15. The memory device of claim 14, wherein the selectable groups of the normally used memory cells are individually selectable based on column select (CS) signals.

16. The memory device of claim 14, wherein the selectable groups of the redundant memory cells are individually selectable based on redundant column select (RCS) signals.

17. The memory device of claim 14, wherein each of the plurality of normally used memory cell sub-arrays and the another sub-array each include an equal quantity of the selectable groups.

18. The method of claim 14, wherein each of the plurality of normally used memory cell sub-arrays includes a quantity of selectable groups and the another sub-array includes a quantity of selectable groups differing by one in quantity from the quantity of the selectable groups of the normally used memory cell sub-arrays.

19. A memory device, including:

a plurality of substantially equally sized sub-arrays of normally used memory cells and redundant memory cells, wherein groups of memory cells in a first portion of the sub-arrays are each selectable by a first quantity of select signals and a second portion of the sub-arrays are each selectable by a second quantity of select signals; and

wherein one of the plurality of sub-arrays partially includes all of the groups of the redundant memory cells selectable by respective redundant select signals.

20. The memory device of claim 19, wherein the first quantity of select signals and the second quantity of select signals are equal.

21. The memory device of claim 19, wherein the first quantity of select signals and the second quantity of select signals differ by one select signal.

22. The memory device of claim 19, wherein the selectable groups of the normally used memory cells are individually selectable based on column select (CS) signals.

23. The memory device of claim 19, wherein the selectable groups of the redundant memory cells are individually selectable based on redundant column select (RCS) signals.

24. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, the memory device including a plurality of sub-arrays including groups of selectable normally used memory cells and groups of selectable redundant memory cells, wherein each of the plurality of sub-arrays includes a substantially equal quantity of groups and all of the groups of selectable redundant memory cells are resident in one of the plurality of sub-arrays.

25. The electronic system of claim 24, wherein the quantity of groups in each of the sub-arrays is equal.

26. The electronic system of claim 24, wherein the quantity of groups in each of the plurality of sub-arrays varies by only one group from any quantity of groups in any other one of the plurality of sub-arrays.

27. The electronic system of claim 24, wherein the selectable groups of the normally used memory cells are individually selectable based on column select (CS) signals.

28. The electronic system of claim 24, wherein the selectable groups of the redundant memory cells are individually selectable based on redundant column select (RCS) signals.