Temperature sensing circuit and semiconductor memory device using the same

• US 20080291969A1
• Filed: 12/28/2007
• Published: 11/27/2008
• Est. Priority Date: 05/21/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Chu, Gyo Soo
• Granted Patent: US 8,033,720 B2
• Time in Patent Office: Days
• US Class Current: 374/178
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A temperature sensing circuit comprises a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation, and a comparison unit for comparing the reference voltage to the variable voltage, detecting an ambient temperature and generating a temperature detecting signal.

Claims

1. A temperature sensing circuit comprising:

a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation; and

a comparison unit for comparing the reference voltage to the variable voltage, detecting an ambient temperature and generating a temperature detecting signal.

2. The temperature sensing circuit of claim 1, wherein the temperature sensing unit includes:

a reference voltage generating unit for dividing a driving voltage and generating the reference voltage;

a control voltage generating unit for generating a first voltage in response to the reference voltage; and

an amplifying unit for generating the variable voltage in response to the first voltage.

3. The temperature sensing circuit of claim 2, wherein the reference voltage generating unit includes:

a plurality of voltage dividing elements in series connected between a driving voltage supply terminal for receiving the driving voltage and a first node; and

an enable element connected between the first node and a ground voltage level in order to enable an operation of the voltage dividing elements in response to a first enable signal.

4. The temperature sensing circuit of claim 3, wherein the control voltage generating unit includes:

a first level controlling element connected between the driving voltage supply terminal and a second node; and

a first temperature element connected between the first node and the second node to generate the first voltage in response to the reference voltage.

6. The temperature sensing circuit of claim 4, wherein the amplifying unit includes:

a second level controlling element connected between the driving voltage supply terminal and a third node;

a second temperature element connected between the first node and the third node and generating a second voltage in response to the first voltage;

a third level controlling element connected between the driving voltage supply terminal and a fourth node; and

a second temperature element connected between the first node and the fourth node to generate the variable voltage in response to the second voltage.

7. The temperature sensing circuit of claim 1, wherein the comparison unit includes a differential amplifier.

8. The temperature sensing circuit of claim 1, further comprising a temperature sensing control unit configured to receive a first enable signal and a period signal and generate a second enable signal for enabling the temperature sensing unit and the comparison unit every period of the period signal.

9. The temperature sensing circuit of claim 8, wherein the temperature sensing control unit generates a counter pulse for sampling the temperature detecting signal.

10. The temperature sensing circuit of claim 9, further comprising a flag signal generating unit for sampling the temperature detecting signal in response to the counter pulse and generating a flag signal having temperature information, wherein the flag signal is enabled when the sampled temperature detecting signal is enabled at least once.

11. The temperature sensing circuit of claim 1, further comprising a temperature sensing control unit which includes:

a first logic element for performing a first logic operation to a first enable signal and a period signal;

a delay unit for generating a second enable signal, which is enabled every period of the period signal, by delaying an output signal of the first logic element; and

a logic unit for generating a counter pulse for sampling the temperature detecting signal by performing a second logic operation to an output signal of the first logic element and another signal which is produced by delaying the output signal of the first logic element.

12. The temperature sensing circuit of claim 11, further comprising:

a flag signal generating unit including a counting unit configured to receive the temperature detecting signal and generate a plurality of counting signals in response to the counter pulse; and

a signal processing unit configured to receive the plurality of counting signals and then generate a flag signal having temperature information therein, wherein the flag signal is enabled when all of the plurality of counting signals are enabled.

13. The temperature sensing circuit of claim 12, wherein the counting unit is initialized in response to the first enable signal.

5. The temperature sensing circuit of claim 5, wherein the amplifying unit includes:

a second level controlling element connected between the driving voltage supply terminal and a third node; and

a second temperature element connected between the first node and the third node to generate the variable voltage in response to the first voltage.

14. A semiconductor memory device comprising:

a sensing circuit, including;

a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation; and

a comparison unit for comparing the reference voltage to the variable voltage, detecting an ambient temperature and generating a temperature detecting signal;

a control circuit for performing a control operation based on temperature information in the temperature detecting signal; and

a temperature sensing control unit configured to receive a first enable signal and a period signal and generate a second enable signal for enabling the temperature sensing unit and the comparison unit every period of the period signal.

15. The semiconductor memory device of claim 14, wherein the temperature sensing unit includes:

a reference voltage generating unit for dividing a driving voltage and generating the reference voltage;

a control voltage generating unit for generating a first voltage in response to the reference voltage; and

an amplifying unit for generating the variable voltage in response to the first voltage.

16. The semiconductor memory device of claim 15, wherein the reference voltage generating unit includes:

a plurality of voltage dividing elements in series connected between a driving voltage supply terminal for receiving the driving voltage and a first node; and

an enable element connected between the first node and a ground voltage level in order to enable an operation of the voltage dividing elements in response to a first enable signal.

17. The semiconductor memory device of claim 16, wherein the control voltage generating unit includes:

a first level controlling element connected between the driving voltage supply terminal and a second node; and

a first temperature element connected between the first node and the second node to generate the first voltage in response to the reference voltage.

18. The semiconductor memory device of claim 17, wherein the amplifying unit includes:

a second level controlling element connected between the driving voltage supply terminal and a third node; and

a second temperature element connected between the first node and the third node to generate the variable voltage in response to the first voltage.

19. The semiconductor memory device of claim 17, wherein the amplifying unit includes:

a second level controlling element connected between the driving voltage supply terminal and a third node;

a second temperature element connected between the first node and the third node and generating a second voltage in response to the first voltage;

a third level controlling element connected between the driving voltage supply terminal and a fourth node; and

a second temperature element connected between the first node and the fourth node to generate the variable voltage in response to the second voltage.

20. The semiconductor memory device of claim 14, wherein the temperature sensing control unit generates a counter pulse for sampling the temperature detecting signal.

21. The semiconductor memory device of claim 20, further comprising a flag signal generating unit for sampling the temperature detecting signal in response to the counter pulse and generating a flag signal having temperature information, wherein the flag signal is enabled when the sampled temperature detecting signal is enabled at least once.

22. The semiconductor memory device of claim 14, further comprising a temperature sensing control unit which includes:

a first logic element for performing a first logic operation to a first enable signal and a period signal;

a delay unit for generating a second enable signal, which is enabled every period of the period signal, by delaying an output signal of the first logic element; and

a logic unit for generating a counter pulse for sampling the temperature detecting signal by performing a second logic operation to an output signal of the logic element and a signal which is produced by delaying the output signal of the logic element.

23. The semiconductor memory device of claim 22, further comprising:

a flag signal generating unit including a counting unit configured to receive the temperature detecting signal and generate a plurality of counting signals in response to the counter pulse; and

a signal processing unit configured to receive the plurality of counting signals and then generate a flag signal having temperature information therein, wherein the flag signal is enabled when all of the plurality of counting signals are enabled.

24. The semiconductor memory device of claim 23, wherein the counting unit is initialized in response to the first enable signal.

25. The semiconductor memory device of claim 14, wherein the control circuit is a circuit for controlling a self refresh operating period by using the temperature information.