Radio Receiver Including a Delay-Locked Loop (DLL) for Phase Adjustment

• US 20080292022A1
• Filed: 05/21/2007
• Published: 11/27/2008
• Est. Priority Date: 05/21/2007
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Blum, Gregory
• Granted Patent: US 7,817,750 B2
• Time in Patent Office: Days
• US Class Current: 375/317
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0036 using a recovered symbol clock
• CPC Class Codes: H04L 2027/0053 Closed loops
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0069 Loop filters
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits

Abstract

A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. In one embodiment, a receiver circuit can include: (i) a voltage-controlled oscillator (VCO) for providing a reference clock; (ii) a delay element that can receive the reference clock and provide a delay adjustment signal; (iii) a first channel for receiving a radio signal and providing a recovered radio signal from the radio signal and the delay adjustment signal, where the first channel includes a first mixer and a first filter; and (iv) a second channel for receiving the radio signal and a phase adjustment signal derived from the delay adjustment signal and for providing a delay control signal to the delay element from the radio signal and the phase adjustment signal, where the second channel includes a second mixer and a second filter.

Claims

1. A receiver circuit, comprising:

a) a voltage-controlled oscillator (VCO) configured to provide a reference clock;

b) a delay element configured to receive said reference clock and provide a delay adjustment signal;

c) a first channel configured to receive a radio signal and provide a recovered radio signal from said radio signal and said delay adjustment signal, said first channel comprising a first mixer and a first filter; and

d) a second channel configured to receive said radio signal and a phase adjustment signal derived from said delay adjustment signal, and provide a delay control signal to said delay element from said radio signal and said phase adjustment signal, said second channel comprising a second mixer and a second filter.

2. The receiver circuit of claim 1, further comprising a phase-locked loop (PLL) coupled to a DLL and said VCO, said PLL being configured to provide said reference clock, wherein said DLL comprises said delay element and said second channel.

3. The receiver circuit of claim 1, comprising a phase shifter configured to receive said delay adjustment signal and provide said phase adjustment signal.

4. The receiver circuit of claim 3, wherein when said radio signal has a form A(t)cos(ω

_ct), said recovered radio signal comprises a form ½

BA(t), and said reference clock has a form B cos(ω

₁t).

5. The receiver circuit of claim 1, wherein each of said first and second filters comprises a low-pass filter.

6. The receiver circuit of claim 1, wherein said phase adjustment signal differs in phase from said delay adjustment signal by about 90°

.

7. The receiver circuit of claim 1, further comprising a reset circuit configured to reset said delay control signal at a predetermined time.

8. The receiver circuit of claim 7, wherein said predetermined time comprises when said delay control signal corresponds to a delay adjustment signal having a cos(0) or a cos(2π

) value.

9. The receiver circuit of claim 7, wherein said predetermined time comprises a fixed interval.

10. The receiver circuit of claim 7, wherein said reset circuit comprises replica delay line circuitry and a comparator.

11. The receiver circuit of claim 7, wherein said reset circuit comprises a reset switch coupled to a low-pass filter.

12. A method of recovering a modulated radio signal, comprising the steps of:

a) generating a delay adjustment signal by delaying a reference clock by a configurable delay;

b) phase-shifting said delay adjustment signal to provide a phase adjustment signal;

c) generating a delay control signal from a received radio signal and said phase adjustment signal; and

d) recovering said modulated radio signal from said received radio signal and said delay adjustment signal.

13. The method of claim 12, wherein the step of generating said delay adjustment signal comprises using a delay element in a delay-locked loop (DLL).

14. The method of claim 12, wherein when said received radio signal has a form A(t)cos(ω

_ct), said modulated radio signal comprises a form ½

BA(t), and said reference clock has a form B cos(ω

₁t).

15. The method of claim 12, wherein the step of phase-shifting said delay adjustment signal comprises phase-shifting by about 90°

.

16. The method of claim 12, further comprising resetting said delay control signal.

17. A method of synchronizing a reference clock to a radio signal, comprising the steps of:

a) receiving said radio signal in first and second channels, said first channel providing a recovered radio signal using a delay adjustment signal, and said second channel providing a delay control signal using a phase adjustment signal derived from said delay adjustment signal;

b) controlling a delay element using said delay control signal, said delay element receiving a reference clock and providing said delay adjustment signal; and

c) resetting said delay control signal at a predetermined time.

18. The method of claim 17, wherein each of said first and second channels comprises a mixer and a low-pass filter.

19. The method of claim 17, wherein said predetermined time comprises when said delay control signal corresponds to a delay adjustment signal having a cos(0) or a cos(2π

) value.

20. The method of claim 19, wherein the step of resetting comprises comparing a channel circuit output to a predetermined maximum value corresponding to said cos(2π

) value, and setting said channel circuit output to a predetermined minimum value corresponding to said cos(0) value.

21. The method of claim 17, wherein said predetermined time comprises a fixed interval.

22. A circuit for resetting a delay in a delay-locked loop (DLL), comprising:

a) a channel configured to receive a radio signal and provide a delay control signal from said radio signal and a phase adjustment signal, said channel comprising a mixer and a filter, wherein said phase adjustment signal is derived from a delay adjustment signal, and wherein said DLL comprises a delay element configured to provide said delay adjustment signal from a reference clock; and

b) a reset circuit configured to reset said delay control signal at a predetermined time.

23. The circuit of claim 22, wherein said reset circuit comprises:

a) first and second replica delay lines; and

b) a comparator coupled to an output of said filter and an output of said second replica delay line, wherein said comparator is configured to generate a pulse for resetting a switch to reset said delay control signal to a value of a delay control for said first replica delay line, said pulse being generated when an output of said first replica delay line has a cos(0) value, and an output of said second replica delay line has a cos(2π

) value.

24. The circuit of claim 22, wherein said reset circuit comprises a switch coupled to said filter, said switch being configured to reset said filter at said predetermined time.

25. The circuit of claim 24, wherein said switch is configured to substantially discharge a capacitor in said filter when said switch is closed.