POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS

• US 20080293233A1
• Filed: 07/10/2008
• Published: 11/27/2008
• Est. Priority Date: 07/27/2005
• Status: Active Grant

• Current Assignee: Anil Kumar Chinthakindi, Anthony Kendall Stamper, Douglas Duane Coolbaugh, Jeffrey Peter Gambino, John Edward Florkey, Kunal Vaed, Zhong-Xiang He
• Original Assignee: Anil Kumar Chinthakindi, Anthony Kendall Stamper, Douglas Duane Coolbaugh, Jeffrey Peter Gambino, John Edward Florkey, Kunal Vaed, Zhong-Xiang He
• Inventors: He, Zhong-Xiang, Gambino, Jeffrey Peter, Stamper, Anthony Kendall, Vaed, Kunal, Coolbaugh, Douglas Duane, Chinthakindi, Anil Kumar, Florkey, John Edward
• Granted Patent: US 7,732,294 B2
• Time in Patent Office: Days
• US Class Current: 438/612
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate having at least one metal wiring level within the substrate;

depositing an insulative layer on a surface of the substrate;

forming an inductor within the insulative layer using a patterned plate process; and

forming a wire bond pad within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

2. The method of claim 1, before depositing the insulative layer on the surface of the substrate, further comprising:

depositing a dielectric capping layer on the surface of the substrate.

3. The method of claim 2, wherein forming the inductor further comprises:

forming an at least one opening within the insulative layer;

depositing a liner on the surface of the substrate and on a surface within the at least one opening;

depositing a seed layer on a surface of the liner;

removing a portion of the seed layer from the surface of the liner, leaving the seed layer on the surface of the liner within the at least one opening within the insulative layer;

depositing a conductive material within the at least one opening within the insulative layer, such that the conductive material extends above the surface of the substrate; and

planarizing the surface of the substrate to remove excess conductive material extending beyond the surface of the substrate.

4. The method of claim 3, between forming the at least one opening within the insulative layer and depositing the liner over the surface of the substrate, further comprising:

removing the dielectric capping layer beneath the at least one opening within the insulative layer down to the surface of the substrate;

5. The method of claim 3, between removing the portion of the seed layer from the liner and depositing the conductive material, further comprising:

depositing a layer of photoresist over the surface of the substrate; and

forming an opening within the layer of photoresist above and adjacent to the at least one opening within the insulative layer to expose the seed layer within the at least one opening, wherein the opening within the insulative layer has a diameter smaller than a diameter of the opening within the layer of photoresist above and adjacent to the at least one at least one opening within the insulative layer.

6. The method of claim 5, following planarizing the surface of the substrate, further comprising:

removing the layer of photoresist; and

removing the liner from the surface of the substrate.