PROGRAMMABLE SYSTEM-ON-CHIP HUB

• US 20080294806A1
• Filed: 03/31/2008
• Published: 11/27/2008
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Harrington, Drew Marshall, Swindle, Scott Allen
• Granted Patent: US 8,572,297 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A Programmable System on a Chip Hub (PHUB) is configured to enable master processing elements within the PHUB to simultaneously access peripherals on different busses. The master processing elements include a Central Processing Unit (CPU) interface configured to decode addresses received from a CPU and configure the PHUB to connect signaling from the CPU to one of the multiple busses associated with the address. A second one of the master processing elements is a Direct Memory Access Controller (DMAC) source engine configured to conduct Direct Memory Access (DMA) reads. A third one of the master processing elements is a DMAC destination engine configured to conduct DMA writes independently of the CPU interface.

Claims

1. A connection hub, comprising:

one or more master processing elements;

multiple different separately accessible busses; and

a bus connection circuit configured to enable the master processing elements to simultaneously access the different busses.

2. The connection hub according to claim 1 further comprising multiple independently operating bus interface circuits each associated with a different one of the multiple busses.

3. The connection hub according to claim 2 wherein the bus interface circuits ground any of the busses that is not being accessed by one of the master processing elements.

4. The connection hub according to claim 1 wherein one or more of the master processing elements is a Central Processing Unit (CPU) interface configured to decode an address received from a CPU and configure the bus connection circuit to connect signaling received from the CPU to one of the multiple busses associated with the address.

5. The connection hub according to claim 1 wherein a first one of the master processing elements is a Direct Memory Access Controller (DMAC) source engine configured to conduct Direct Memory Access (DMA) reads from peripheral devices connected to the busses and a second one of the master processing elements is a DMAC destination engine configured to conduct DMA writes to peripheral devices connected to the busses.

6. The connection hub according to claim 5 further comprising a first-in first-out (FIFO) coupled between the DMAC source engine and the DMAC destination engine configured to transfer data read by the DMAC source engine from one of the peripherals to the DMAC destination engine for writing to one of the peripherals.

7. The connection hub according to claim 5 wherein the DMAC source engine and DMAC destination engine each determine which peripherals and which busses to access according to addresses contained in programmable transaction descriptors.

8. The connection hub according to claim 1 wherein the master processing elements include look-up tables that identify particular peripherals and busses associated with received address values.

9. The connection hub according to claim 1 further comprising configuration registers that programmably determine how many busses are coupled to the connection hub, the number of peripherals connected to the busses, and the word lengths of addresses and data transferred over the busses.

10. The connection hub according to claim 1 wherein the bus connection circuit establishes connection paths between the master processing elements and peripherals on the busses in a single bus cycle without ever buffering information carried over the connection paths.

11. The apparatus according to claim 1 further comprising a multiplexer configured to force unused busses to static zero values.

12. An apparatus, comprising:

a Central Processing Unit (CPU) interface configured to communicate with a CPU;

a Direct Memory Access Controller (DMAC) configured to conduct Direct Memory Accesses (DMAs) independently of the CPU; and

a bus connection circuit coupled to multiple different separately accessible busses and configured to couple the CPU and the DMAC to different busses at the same time.

13. The apparatus according to claim 12 wherein the CPU interface and the DMAC each include separate arbitration logic configured to separately identify available busses and configure the bus connection circuit to establish connections between the CPU interface or DMAC and the available busses.

14. The apparatus according to claim 13 wherein the CPU interface and the DMAC are assigned higher priority levels for different associated busses and the arbitration logic in the CPU interface and DMAC is configured to send request pause signals to other devices with lower priority levels that are using the associated busses, the request pause signal causing the other devices to stop communicating over the associated busses so the CPU interface or DMAC can transfer information over the associated buses.

15. The apparatus according to claim 13 wherein the arbitration logic in the CPU interface and the DMAC generates bus access active signals and bus numbers associated with the busses, the bus access active signals and bus numbers used by the bus connection circuit for connecting the CPU interface and DMAC to the buses associated with the bus number.

16. The apparatus according to claim 15 further comprising bus interface circuits associated with each of the busses, the bus interface circuits connecting one of the CPU interface or DMAC to the associated busses according to the bus access active signals and the bus numbers received from the CPU interface and the DMAC.

17. The apparatus according to claim 12 wherein the bus connection circuit includes:

encoders that generate output signals that identify which of the CPU interface, DMAC, or ground to connect to associated busses;

multiplexers that selectively connect either the CPU interface, the DMAC, or ground to the associated busses according to the output signals from the encoders; and

a delay circuit that prevents the encoders from changing or generating glitches on the output signal while the encoders determine which of CPU interface, DMAC, or ground to connect to the associated busses.

18. A programmable system on a chip, comprising:

a Central Processing Unit (CPU);

different peripheral devices; and

a hub that programmably couples the CPU with different peripheral devices over selected ones of the multiple different buses.

19. The programmable system on a chip according to claim 18 wherein the hub further comprises:

a Direct Memory Access Controller (DMAC) source engine configured to conduct read operations with the different peripherals over the different busses independently from the CPU; and

a separate DMAC destination engine configured to conduct write operations with the different peripherals over the different busses independently from the CPU and DMAC source engine.

20. The programmable system on a chip according to claim 19 further comprising:

an array of digital blocks; and

a programmable interconnect matrix including horizontal channels that programmably couple different groups of one or more digital blocks together and segmentation elements that programmably interconnect different horizontal channels together, the hub programmably coupling the CPU, the DMAC source engine, and the DMAC destination engine to the digital blocks.