Flash Memory System with Management of Housekeeping Operations

• US 20080294814A1
• Filed: 05/24/2007
• Published: 11/27/2008
• Est. Priority Date: 05/24/2007
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Gorobets, Sergey Anatolievich
• Application Number:
  US11/753,491
• Publication Number:
  US 20080294814A1
• Time in Patent Office: Days
• US Class Current: 710/62
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test

Abstract

A flash re-programmable, non-volatile memory system is operated to disable foreground execution of housekeeping operations, such as wear leveling and data scrub, in the when operation of the host would be excessively slowed as a result. One or more characteristics of patterns of activity of the host are monitored by the memory system in order to determine when housekeeping operations may be performed without significantly degrading the performance of the memory system, particularly during writing of data from the host into the memory.

Claims

1. A memory system adapted to be removably connected with a host system, comprising:

an array of re-programmable non-volatile memory cells organized into blocks of memory cells wherein the memory cells of the individual blocks are simultaneously erasable,

a controller including a microprocessor that operates to;

note when a housekeeping operation not required for execution of a command received from a host has been asserted,

determine at least one parameter of activity of the host, and

if the determined at least one parameter meets at least one predefined condition, execution of the housekeeping operation is not enabled, but

if the determined at least one parameter does not meet the predefined condition, the housekeeping operation is enabled for execution.

2. The memory system of claim 1, wherein the controller additionally operates, when execution of the housekeeping operation is enabled, to execute at least one portion of the housekeeping operation while the memory system sends a busy status indication to the host, thereby to execute the housekeeping operation in the foreground.

3. The memory system of claim 1, wherein the controller additionally operates, when execution of the housekeeping operation is enabled, to execute the housekeeping operation while the memory system is not sending a busy status indication to the host, thereby to execute the housekeeping operation in the background.

4. The memory system of claim 1, wherein the housekeeping operation includes rewriting data from one location in the memory system to another location in the memory system.

5. The memory system of claim 3, wherein the housekeeping operation data rewriting is performed as part of either a wear leveling or scrub housekeeping operation.

6. The memory system of claim 1, wherein determining at least one parameter of activity of the host includes monitoring said at least one parameter during execution by the memory system of one of the commands received from the host.

7. The memory system of claim 1, wherein said at least one parameter is a count of a number of logical units of data transferred into or out of the memory as a result of executing a single host command, said at least one predefined condition includes a threshold number of units of data, wherein the one parameter meets the one condition when the count is less than the threshold number and does not meet the one condition when count is greater than the threshold number.

8. The memory system of claim 1, wherein said at least one parameter is a logical address difference between a beginning of data being transferred in response to the command received from the host and an end of data transferred during execution of a previous command received from the host, said at least one predefined condition includes a predefined address difference, wherein the one parameter meets the one condition when the logical address difference is greater than the predefined address difference and does not meet the one condition when the logical address difference is greater than the predefined address difference.

9. The memory system of claim 6, wherein said at least one parameter includes a duration of time of response by the host to the memory system after the memory system indicates to the host that the memory system is not busy, said at least one predefined condition includes a predefined time increment, wherein the one parameter meets the one predefined condition when the time duration is less than the predefined time increment and does not meet the one predefined condition when the time duration is greater than the predefined time increment.

10. The memory system of claim 2, wherein the housekeeping operation includes wear leveling.

11. The memory system of claim 2, wherein the housekeeping operation includes scrub.

12. The memory system of claim 3, wherein the housekeeping operation includes wear leveling.

13. The memory system of claim 3, wherein the housekeeping operation includes scrub.

14. The memory system of claim 1, wherein the current received command is one of a group of commands that individually include data read and data write.

15. The memory system of claim 14, wherein the group of commands additionally includes erase of defined blocks of the memory.