ARBITRATION SYSTEM HAVING A PACKET MEMORY AND METHOD FOR MEMORY RESPONSES IN A HUB-BASED MEMORY SYSTEM

• US 20080294862A1
• Filed: 07/09/2008
• Published: 11/27/2008
• Est. Priority Date: 02/05/2004
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Application Number:
  US12/170,329
• Publication Number:
  US 20080294862A1
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers and stores the memory request identifiers. A packet tracker receives remote memory responses and associates each remote memory response with a memory request identifier and removes the memory request identifier from the packet memory. A multiplexor receives remote memory responses and local memory responses. The multiplexor selects an output responsive to a control signal. Arbitration control logic is coupled to the multiplexor and the packet memory and develops the control signal to select a memory response for output.

Claims

1. A memory hub, comprising:

an electronic component operable to receive memory requests including local memory requests directed to memory devices connected directly to the memory hub and remote memory requests directed to memory devices coupled to other memory hubs;

a multiplexor being operable to couple either remote memory responses that are received responsive to the remote memory requests or local memory responses that are received responsive to the local memory requests to an output responsive to a control signal; and

arbitration control logic coupled to the multiplexor and being operable to determine recency of the memory requests corresponding to the received remote memory responses and the local memory responses and to generate the control signal based on the determination.

34. The memory hub of claim 1 wherein the arbitration control logic generates the control signal based on an oldest of the memory requests corresponding to the received remote memory responses and the local memory responses.

35. The memory hub of claim 1 wherein the electronic component comprises a memory request decoder.

36. The memory hub of claim 1 wherein each of the local and remote memory responses comprise data and a header identifying a memory request corresponding to the memory response.

37. The memory hub of claim 1 wherein each of the remote memory responses comprises a memory request identifier corresponding to the memory request to which the remote memory request is responsive, and wherein the arbitration logic in the memory hub is operable to determine recency of the remote memory requests corresponding to the received remote memory responses based on the memory request identifiers in the remote memory responses.

2-33. -33. (canceled)

38. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the memory devices, the memory hub comprising;

an electronic component operable to receive memory requests including local memory requests directed to memory devices connected directly to the memory hub and remote memory requests directed to memory devices coupled to other memory hubs;

a multiplexer operable to couple from the memory hub either remote memory responses that are received by the memory hub responsive to the remote memory requests or local memory responses that are received by the memory hub from at least one of the plurality of memory devices responsive to the local memory requests; and

arbitration control logic coupled to the multiplexer and being operable to determine recency of the memory requests corresponding to the received remote memory responses and the local memory responses and to generate the control signal based on the determination.

39. The memory module of claim 38 wherein each of the memory devices comprise an SDRAM.

40. The memory module of claim 38 wherein the arbitration control logic generates the control signal based on an oldest of the memory requests corresponding to the received remote memory responses and the local memory responses.

41. The memory module of claim 38 wherein the electronic component comprises a memory request decoder.

42. The memory module of claim 38 wherein each of the local and remote memory responses comprise data and a header identifying a memory request corresponding to the memory response.

43. The memory module of claim 38 wherein each of the remote memory responses comprises a memory request identifier corresponding to the memory request to which the remote memory request is responsive, and wherein the arbitration logic in the memory hub is operable to determine recency of the remote memory requests corresponding to the received remote memory responses based on the memory request identifiers in the remote memory responses.

44. A processor-based system, comprising:

a processor;

a system controller coupled to the processor, the system controller including a memory hub controller;

an input device coupled to the processor through the system controller;

an output device coupled to the processor through the system controller;

a storage device coupled to the processor through the system controller;

a plurality of memory modules, each memory module being coupled to adjacent memory modules through a communication link, at least one of the memory modules being coupled to the memory hub controller through a communications link, and each memory module comprising;

a plurality of memory devices; and

a memory hub coupled to the memory devices in the memory module and to the communication link, the memory hub comprising;

an electronic component operable to receive memory requests including local memory requests directed to memory devices in the same memory module and remote memory requests directed to memory devices in other memory modules;

a multiplexer operable to couple from the memory hub either remote memory responses that are received by the memory hub in the memory module from other memory modules or local memory responses that are received by the memory hub from at least one of the plurality of memory devices in the same memory module; and

arbitration control logic coupled to the multiplexer and being operable to determine recency of the memory requests corresponding to the received remote memory responses and the local memory responses and to generate the control signal based on the determination.

45. The processor-based system of claim 44 wherein each of the memory devices comprise an SDRAM.

46. The processor-based system of claim 44 wherein the arbitration control logic generates the control signal based on an oldest of the memory requests corresponding to the received remote memory responses and the local memory responses.

47. The processor-based system of claim 44 wherein the electronic component comprises a memory request decoder.

48. The processor-based system of claim 44 wherein each of the local and remote memory responses comprise data and a header identifying a memory request corresponding to the memory response.

49. The processor-based system of claim 44 wherein each of the remote memory responses comprises a memory request identifier corresponding to the memory request to which the remote memory request is responsive, and wherein the arbitration logic in the memory hub is operable to determine recency of the remote memory requests corresponding to the received remote memory responses based on the memory request identifiers in the remote memory responses.

50. In a memory system including a plurality of memory modules, each memory module including a memory hub coupled to memory devices, a method of processing and forwarding memory responses in the memory hub of each memory module, comprising:

receiving memory requests, the memory requests including local memory requests directed to memory devices connected to the memory hub and remote memory requests directed to memory devices coupled to memory hubs in other memory modules;

storing local memory responses received from the memory devices in response to the local memory requests;

storing remote memory responses received from the other memory modules in response to the remote memory requests;

applying in at least one hub an arbitration algorithm based on the ages of the stored memory request identifiers to determine an order in which the stored local and remote memory responses are forwarded; and

forwarding the local and remote memory responses upstream according to the determined order.

51. The method of claim 50 wherein each of the local and remote memory responses comprise data and a header identifying a memory request corresponding to the memory response.

52. The method of claim 50, further comprising generating a control signal to indicate the order based on an oldest memory request.

53. The method of claim 50, further comprising generating a control signal such that if an oldest memory request is a local memory request, a local memory response is forwarded.