MODELING ASYNCHRONOUS BEHAVIOR FROM PRIMARY INPUTS AND LATCHES

• US 20080295052A1
• Filed: 07/07/2008
• Published: 11/27/2008
• Est. Priority Date: 02/23/2006
• Status: Active Grant

• Current Assignee: Bradley S. Nelson, Yee Ja, Zoltan T. Hidvegi
• Original Assignee: Bradley S. Nelson, Yee Ja, Zoltan T. Hidvegi
• Inventors: Nelson, Bradley S., Ja, Yee, Hidvegi, Zoltan T.
• Granted Patent: US 7,885,801 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.

Claims

1. A method of modeling asynchronous behavior of a circuit stored as a netlist in a computer system, comprising:

identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic; and

modifying the stored netlist by inserting additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic.

2. The method of claim 1 wherein the output of the additional logic is selectively responsive to a user-controlled skew enable input.

3. The method of claim 1 wherein the delayed output from the driving element is delayed with respect to the present driving element output by a number of cycles n which is a minimum of a send clock period of the driving element and a receive clock period of the downstream logic.

4. The method of claim 1 wherein the additional logic includes:

a random value generator having an output;

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the output of the random value generator, the multiplexer further having an output which drives the downstream logic;

an XOR gate having at least two inputs, a first input of the XOR gate being connected to the present output from the driving element, and a second input of the XOR gate being connected to the delayed output from the driving element; and

an AND gate having at least two inputs, a first input of the AND gate being connected to an output of the XOR gate, and a second input of the AND gate being connected to a user-controlled skew enable signal, the AND gate further having an output which controls a select line of the multiplexer.

5. The method of claim 1 wherein the additional logic includes:

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the delayed output from the driving element, the multiplexer further having an output which drives the downstream logic;

a random value generator having an output; and

an AND gate having at least two inputs, a first input of the AND gate being connected to the output of the random value generator, and a second input of the AND gate being connected to a user-controlled skew enable signal, the AND gate further having an output which controls a select line of the multiplexer.

6. The method of claim 1 wherein the additional logic includes:

a random value generator having an output;

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the delayed output from the driving element, the multiplexer further having a select line controlled by a user-controlled skew enable signal; and

a ONE OFF gate having at least three inputs, a first input of the ONE OFF gate being connected to the present output from the driving element, a second input of the ONE OFF gate being connected to the output of the random value generator, and a third input of the ONE OFF gate being connected to an output of the multiplexer, the ONE OFF gate further having an output which drives the downstream logic.

7. A computer system comprising:

one or more processors which process program instructions;

a memory device connected to said one or more processors; and

program instructions residing in said memory device for modeling asynchronous behavior of a circuit stored as a netlist in said memory device by identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic, and modifying the stored netlist to insert additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic.

8. The computer system of claim 7 wherein the output of the additional logic is selectively responsive to a user-controlled skew enable input.

9. The computer system of claim 7 wherein the delayed output from the driving element is delayed with respect to the present driving element output by a number of cycles n which is a minimum of a send clock period of the driving element and a receive clock period of the downstream logic.

10. The computer system of claim 7 wherein the additional logic includes:

a random value generator having an output;

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the output of the random value generator, the multiplexer further having an output which drives the downstream logic;

an XOR gate having at least two inputs, a first input of the XOR gate being connected to the present output from the driving element, and a second input of the XOR gate being connected to the delayed output from the driving element; and

an AND gate having at least two inputs, a first input of the AND gate being connected to an output of the XOR gate, and a second input of the AND gate being connected to a user-controlled skew enable signal, the AND gate further having an output which controls a select line of the multiplexer.

11. The computer system of claim 7 wherein the additional logic includes:

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the delayed output from the driving element, the multiplexer further having an output which drives the downstream logic;

a random value generator having an output; and

an AND gate having at least two inputs, a first input of the AND gate being connected to the output of the random value generator, and a second input of the AND gate being connected to a user-controlled skew enable signal, the AND gate further having an output which controls a select line of the multiplexer.

12. The computer system of claim 7 wherein the additional logic includes:

a random value generator having an output;

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the delayed output from the driving element, the multiplexer further having a select line controlled by a user-controlled skew enable signal; and

a ONE OFF gate having at least three inputs, a first input of the ONE OFF gate being connected to the present output from the driving element, a second input of the ONE OFF gate being connected to the output of the random value generator, and a third input of the ONE OFF gate being connected to an output of the multiplexer, the ONE OFF gate further having an output which drives the downstream logic.

13. A computer program product comprising:

a computer-readable medium; and

program instructions residing in said computer-readable medium to be executed by one or more processors of a computer system for modeling asynchronous behavior of a circuit stored as a netlist in the computer system by identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic, and modifying the stored netlist to insert additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic.

14. The computer program product of claim 13 wherein the output of the additional logic is selectively responsive to a user-controlled skew enable input.

15. The computer program product of claim 13 wherein the delayed output from the driving element is delayed with respect to the present driving element output by a number of cycles n which is a minimum of a send clock period of the driving element and a receive clock period of the downstream logic.

16. The computer program product of claim 13 wherein

a random value generator having an output;

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the output of the random value generator, the multiplexer further having an output which drives the downstream logic;

an XOR gate having at least two inputs, a first input of the XOR gate being connected to the present output from the driving element, and a second input of the XOR gate being connected to the delayed output from the driving element; and

an AND gate having at least two inputs, a first input of the AND gate being connected to an output of the XOR gate, and a second input of the AND gate being connected to a user-controlled skew enable signal, the AND gate further having an output which controls a select line of the multiplexer.

17. The computer program product of claim 13 wherein the additional logic includes:

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the delayed output from the driving element, the multiplexer further having an output which drives the downstream logic;

a random value generator having an output; and

an AND gate having at least two inputs, a first input of the AND gate being connected to the output of the random value generator, and a second input of the AND gate being connected to a user-controlled skew enable signal, the AND gate further having an output which controls a select line of the multiplexer.

18. The computer program product of claim 13 wherein the additional logic includes:

a random value generator having an output;

a multiplexer having at least two inputs, a first input of the multiplexer being connected to the present output from the driving element, and a second input of the multiplexer being connected to the delayed output from the driving element, the multiplexer further having a select line controlled by a user-controlled skew enable signal; and

a ONE OFF gate having at least three inputs, a first input of the ONE OFF gate being connected to the present output from the driving element, a second input of the ONE OFF gate being connected to the output of the random value generator, and a third input of the ONE OFF gate being connected to an output of the multiplexer, the ONE OFF gate further having an output which drives the downstream logic.