MODELING ASYNCHRONOUS BEHAVIOR FROM PRIMARY INPUTS AND LATCHES
First Claim
1. A method of modeling asynchronous behavior of a circuit stored as a netlist in a computer system, comprising:
- identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic; and
modifying the stored netlist by inserting additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic.
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Abstract
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.
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Citations
18 Claims
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1. A method of modeling asynchronous behavior of a circuit stored as a netlist in a computer system, comprising:
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identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic; and modifying the stored netlist by inserting additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computer system comprising:
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one or more processors which process program instructions; a memory device connected to said one or more processors; and program instructions residing in said memory device for modeling asynchronous behavior of a circuit stored as a netlist in said memory device by identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic, and modifying the stored netlist to insert additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer program product comprising:
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a computer-readable medium; and program instructions residing in said computer-readable medium to be executed by one or more processors of a computer system for modeling asynchronous behavior of a circuit stored as a netlist in the computer system by identifying at least one driving element in the stored netlist for the circuit wherein the driving element has an output which is connected to downstream logic, and modifying the stored netlist to insert additional logic whose output is based on a combination of a present output from the driving element, a delayed output from the driving element, and a random value, to drive the downstream logic. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification