Method and apparatus for determining factors for design consideration in yield analysis

• US 20080295063A1
• Filed: 05/22/2008
• Published: 11/27/2008
• Est. Priority Date: 05/24/2007
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Schwarm, Alexander T., Shimshi, Rinat, Svidenko, Vicky, Jawaharlal, Sundar, Nehmadi, Youval
• Granted Patent: US 8,924,904 B2
• Time in Patent Office: Days
• US Class Current: 716/55
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor.

Claims

1. A computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication, the computer-implemented method comprising:

obtaining a geometric characteristic of a defect on a chip;

obtaining design data of the chip, the design data associated with the defect;

determining a criticality factor of the defect based on the geometric characteristic and the design data, the criticality factor indicating a likelihood of the defect to cause a failure of the chip; and

outputting the criticality factor.

2. The computer-implemented method of claim 1, farther comprising:

determining a pattern density of the chip around the defect based on the geometric characteristic and the design data; and

outputting the pattern density.

3. The computer-implemented method of claim 1, wherein obtaining the design data comprises:

defining a search area where the defect is located on the chip; and

marking an open area inside the search area, wherein the open area indicates an area where the defect may cause an open failure, and

determining the criticality factor comprises;

calculating an open failure probability as the criticality factor, wherein the open failure probability is the ratio between the open area and the search area.

4. The computer-implemented method of claim 3, wherein marking the open area comprises:

identifying pattern elements larger than the defect in the search area;

subtracting the identified pattern elements from the original pattern elements in the search area; and

identifying an area that covers the remaining pattern elements as the open area.

5. The computer-implemented method of claim 1, wherein obtaining the design data comprises:

defining a search area on a chip having the defect, wherein the search area indicates an area where the defect is located; and

marking a short area inside the search area, wherein the short area indicates an area where the defect may cause a short failure, and

determining the criticality factor comprises;

calculating a short failure probability as the criticality factor, wherein the short failure probability is the ratio between the short area and the search area.

6. The computer-implemented method of claim 5, wherein marking the short area comprises:

labeling all the separate polygons in an area covering the search area;

enlarging all the labeled separate polygons until neighboring polygons of the labeled separate polygons are overlapped; and

identifying the overlapped area as the short area.

7. The computer-implemented method of claim 1, wherein obtaining the design data comprises:

defining a search area on a chip having the defect, wherein the search area indicates an area where the defect is located;

marking an open area inside the search area, wherein the open area indicates an area where the defect may cause an open failure; and

marking a short area inside the search area, wherein the short area indicates an area where the defect may cause a short failure, and

determining the criticality factor comprises;

calculating an open failure probability that is the ratio between the open area and the search area;

calculating a short failure probability that is the ratio between the short area and the search area; and

calculating the criticality factor based on the open failure probability and the short failure probability.

8. The computer-implemented method of claim 7, wherein calculating the criticality factor comprises:

calculating the criticality factor based on the open failure probability and the short failure probability as follows;

C_f=1−

(1−

P_s)*(1−

P_o)

where C_f represents the criticality factor, P_s represents the short failure probability, and P_o represents the open failure probability.

9. The computer-implemented method of claim 2, wherein obtaining the design data comprises:

defining a search area on a chip having the defect, wherein the search area indicates an area where the defect is located; and

finding a length of all the pattern boundaries inside the search area, and

determining the pattern density comprises;

calculating the ratio between the length of all the pattern boundaries and the search area as the pattern density.

10. The computer-implemented method of claim 1, wherein the geometric characteristic of the defect includes at least one of the size and the location of the defect.

11. The computer-implemented method of claim 1, wherein the design data includes at least one of design layout, on which the defect was found, and routing information of the design layout.

12. An apparatus for determining factors for design consideration in yield analysis of semiconductor fabrication, the apparatus comprising:

a data obtainer to obtain a geometric characteristic of a defect on a chip and design data of the chip, the design data associated with the defect;

a criticality factor calculator, coupled with the data obtainer, to determine a criticality factor of the defect based on the geometric characteristic and the design data, wherein the criticality factor indicating a likelihood of the defect to cause a failure of the chip; and

a criticality factor reporter, coupled with the criticality factor calculator, to output the criticality factor.

13. The apparatus of claim 12, further comprising:

a pattern density calculator, coupled with the data obtainer, to determine a pattern density of the chip around the defect based on the geometric characteristic and the design data; and

a pattern density reporter, coupled with the pattern density calculator, to output the pattern density.

14. The apparatus of claim 12, wherein

the data obtainer is further to define a search area where the defect is located on the chip, and mark an open area inside the search area, the open area indicating an area where the defect may cause an open failure;

and the criticality factor calculator is further to calculate an open failure probability as the criticality factor, the open failure probability being the ratio between the open area and the search area.

15. The apparatus of claim 14, wherein

the data obtainer is further to identify pattern elements larger than the defect in the search area, subtract the identified pattern elements from the original pattern elements in the search area, and identify an area that covers the remaining pattern elements as the open area.

16. The apparatus of claim 12, wherein

the data obtainer is further to define a search area on a chip having the defect, wherein the search area indicates an area where the defect is located, and mark a short area inside the search area, wherein the short area indicates an area where the defect may cause a short failure, and

the criticality factor calculator is further to calculate a short failure probability as the criticality factor, wherein the short failure probability is the ratio between the short area and the search area.

17. The apparatus of claim 16, wherein

the data obtainer is further to label all the separate polygons in an area covering the search area, enlarge all the labeled separate polygons until neighboring polygons of the labeled separate polygons are overlapped, and identify the overlapped area as the short area.

18. The apparatus of claim 12, wherein

the data obtainer is further to define a search area on a chip having the defect, wherein the search area indicates an area where the defect is located, mark an open area inside the search area, wherein the open area indicates an area where the defect may cause an open failure, and mark a short area inside the search area, wherein the short area indicates an area where the defect may cause a short failure, and

the criticality factor calculator is further to calculate an open failure probability that is the ratio between the open area and the search area, calculate a short failure probability that is the ratio between the short area and the search area, and calculate the criticality factor based on the open failure probability and the short failure probability.

19. The apparatus of claim 18, wherein the criticality factor calculator calculates the criticality factor as follows:

C_f=1−

(1−

P_s)*(1−

P_o)

where C_f represents the criticality factor, P_s represents the short failure probability, and P_o represents the open failure probability.

20. A computer readable storage medium containing computer instructions which are executed by a computer to cause the computer to perform a method for determining factors for design consideration in yield analysis of semiconductor fabrication, the method comprising:

obtaining a geometric characteristic of a defect on a chip;

obtaining design data of the chip, the design data associated with the defect;

determining a criticality factor of the defect based on the geometric characteristic and the design data, the criticality factor indicating a likelihood of the defect to cause a failure of the chip; and

outputting the criticality factor.

21. The computer readable storage medium of claim 20, wherein the method further comprises:

determining a pattern density of the chip around the defect based on the geometric characteristic and the design data; and

outputting the pattern density.

22. The computer readable storage medium of claim 21, wherein obtaining the design data comprises:

defining a search area on a chip having the defect, wherein the search area indicates an area where the defect is located;

marking an open area inside the search area, wherein the open area indicates an area where the defect may cause an open failure; and

marking a short area inside the search area, wherein the short area indicates an area where the defect may cause a short failure, and

determining the criticality factor comprises;

calculating an open failure probability that is the ratio between the open area and the search area;

calculating a short failure probability that is the ratio between the short area and the search area; and

calculating the criticality factor based on the open failure probability and the short failure probability as follows;

C_f=1−

(1−

P_s)*(1−

P_o)

where C_f represents the criticality factor, P_s represents the short failure probability, and P_o represents the open failure probability.