FLEXIBLE CIRCUIT

• US 20080295327A1
• Filed: 06/01/2007
• Published: 12/04/2008
• Est. Priority Date: 06/01/2007
• Status: Abandoned Application

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Aeling, Ellen O., David, John R., Jackson, Byron M., Mels, Michael A.
• Application Number:
  US11/756,905
• Publication Number:
  US 20080295327A1
• Time in Patent Office: Days
• US Class Current: 29/832
• CPC Class Codes: H05K 1/0224 Patterned shielding planes, ground planes or power planes H05K1/0253 takes precedence
• CPC Class Codes: H05K 1/0253 Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings H05K1/0251 takes precedence
• CPC Class Codes: H05K 1/0393 Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 1/189 characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/09063 Holes or slots in insulating substrate not used for electrical connections
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09681 Mesh conductors, e.g. as a ground plane
• CPC Class Codes: H05K 2201/0969 Apertured conductors
• CPC Class Codes: H05K 2201/10106 Light emitting diode [LED]
• CPC Class Codes: H05K 2203/063 of preperforated insulating layer
• CPC Class Codes: H05K 2203/1545 Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
• CPC Class Codes: H05K 2203/166 Alignment or registration; Control of registration
• CPC Class Codes: H05K 3/0097 Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: H05K 3/202 using self-supporting metal foil pattern
• CPC Class Codes: H05K 3/303 Surface mounted components, e.g. affixing before soldering, aligning means, spacing means H05K3/32 takes precedence
• CPC Class Codes: H05K 3/386 by the use of an organic polymeric bonding layer, e.g. adhesive
• CPC Class Codes: H05K 3/4635 laminating flexible circuit boards using additional insulating adhesive materials between the boards
• CPC Class Codes: H05K 3/4638 Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

The present application is directed to a method of producing a multilayer circuit. The method comprises providing a first electrically insulating layer comprising apertures through the layer and bonding the first electrically insulating layer with a first conductive layer. The first conductive layer is bonded to the first electrically insulating layer in register to the apertures in the electrically insulating layer and the multilayer circuit is produced at a sustained rate.

In another embodiment, the method comprises providing a second electrically insulating layer and bonding the second electrically insulating layer with the first conductive layer opposite the first electrically insulating layer.

Claims

1. A method of producing a multilayer circuit comprising:

providing a first electrically insulating layer having at least one aperture defined through the layer; and

bonding the first electrically insulating layer with a first conductive layer;

wherein the first conductive layer is bonded to the first electrically insulating layer in register to the apertures in the electrically insulating layer and the multilayer circuit is produced at a sustained rate.

2. The method of claim 1 wherein the conductive layer is bonded to the first electrically insulating layer via a mechanical process.

3. The method of claim 1 comprising providing a first adhesive layer disposed on a first surface of the first insulating layer between the first electrically insulating layer and the first conductive layer.

4. The method of claim 1 wherein the first conductive layer is discontinuous.

5. The method of claim 4 wherein the first conductive layer is in a pattern.

6. The method of claim 5 wherein the pattern is a grid pattern, a series string pattern, a series or parallel pattern, or a series of repeating circuits.

7. The method of claim 1 comprising cutting the multilayer circuit into smaller circuits.

8. The method of claim 1 comprising

providing a second electrically insulating layer;

and

bonding the second electrically insulating layer with the first conductive layer opposite the first electrically insulating layer.

9. The method of claim 8 comprising providing a second adhesive layer disposed on a first surface of the second insulating layer opposite the first conductive layer.

10. The method of claim 9 comprising connecting the second adhesive layer with a second conductive layer opposite the second insulating layer.

11. The method of claim 8 wherein the first conductive layer is continuous.

12. The method of claim 11 wherein the first conductive layer is in a pattern.

13. The method of claim 12 wherein the pattern is a grid pattern.

14. The method of claim 8 wherein the first conductive layer is discontinuous.

15. The method of claim 14 wherein the first conductive layer is in a pattern.

16. The method of claim 15 wherein the pattern is a grid pattern.

17. The method of claim 8 wherein the second conductive layer is continuous.

18. The method of claim 17 wherein the second conductive layer is in a pattern.

19. The method of claim 18 wherein the pattern is a grid pattern.

20. The method of claim 8 wherein the second conductive layer is discontinuous.

21. The method of claim 20 wherein the second conductive layer is in a pattern.

22. The method of claim 21 wherein the pattern is a grid pattern, a series string pattern, a series or parallel pattern, or a series of repeating circuits.

23. The method of claim 1 wherein the first electrically insulating layer is perforated to form apertures arranged in a pattern prior to contacting the first electrically insulating layer to the first conductive layer.

24. The method of claim 23 wherein the multilayer circuit is registered to the pattern in the first electrically insulating layer.

25. The method of claim 1 wherein the first electrically insulating layer is a flexible substrate.

26. The method of claim 1 wherein the first electrically insulating layer is a polymer film.

27. The method of claim 8 wherein the second electrically insulating layer is a flexible substrate.

28. The method of claim 8 wherein the second electrically insulating layer is a polymer film.

29. The method of claim 2 wherein the adhesive is a pressure sensitive adhesive.

30. The method of claim 3 wherein the adhesive is heat activated.

31. The method of claim 1 wherein the first electrically insulating layer is extruded on the first conductive layer.

32. The method of claim 1 wherein the first electrically insulating layer is adhered to the first conductive layer.

33. The method of claim 32 wherein the first electrically insulating layer is laminated to the first conductive layer.

34. The method of claim 1 comprising placing at least one light source on the multilayer circuit on the first electrically insulating layer, opposite the first conductive layer.

35. The method of claim 34 comprising multiple light sources on the multilayer circuit.

36. The method of claim 35 wherein the multiple light sources are arranged in a pattern.

37. The method of claim 36 wherein the pattern is a regular array.

38. The method of claim 34 wherein the light source is a light emitting diode.

39. The method of claim 8 comprising placing at least one light source on the multilayer circuit.

40. The method of claim 1 comprising attaching an electronic component to the first conductive layer.

41. The method of claim 8 comprising attaching an electronic component to the second conductive layer.

42. The method of claim 1 wherein the method runs as speeds greater than 300 feet per minute.

43. The method of claim 1 wherein the method is continuous.

44. The method of claim 34 comprising attaching a transparent layer or a translucent layer over the light source, opposite the multilayer circuit.

45. The method of claim 39 comprising attaching a transparent layer or a translucent layer over the light source, opposite the multilayer circuit.

46. The method of claim 1 wherein the conductive layer has at least one aperture defined through the conductive layer and positioned to align with the at least one aperture in the electrically insulating layer.