Method for Fabricating a Nanoelement Field Effect Transistor with Surrounded Gate Structure

• US 20080296559A1
• Filed: 08/12/2008
• Published: 12/04/2008
• Est. Priority Date: 01/08/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Franz Kreupl, Robert Seidel
• Inventors: Kreupl, Franz, Seidel, Robert
• Granted Patent: US 7,646,045 B2
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/72 On an electrically conducting, semi-conducting, or semi-insulating substrate
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/813 Of specified inorganic semiconductor composition, e.g. periodic table group IV-VI compositions

Abstract

A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in a surface region of the substrate is arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement. A gate-insulating structure covers the periphery of the nanoelement and a gate structure covers the periphery of the gate-insulating structure.

Claims

1. A nanoelement field effect transistor comprising:

a substrate;

a nanotube as a nanoelement on the substrate;

a first source/drain region on and/or in the substrate, the first source/drain region being coupled to a first end portion of the nanoelement;

a second source/drain region on and/or in the substrate, the second source/drain region being coupled to a second end portion of the nanoelement;

a recess in a surface region of the substrate, the recess arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement;

a gate-insulating structure that covers the periphery of the nanoelement; and

a gate structure that covers the periphery of the gate-insulating structure.

2. The nanoelement field effect transistor as claimed in claim 1, wherein the gate-insulating structure comprises silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, and/or hafnium oxide.

3. The nanoelement field effect transistor as claimed in claim 1, wherein the gate structure comprises tantalum nitride, tantalum, molybdenum, nickel, cobalt, titanium nitride, carbon, tungsten, and/or polysilicon.

4. The nanoelement field effect transistor as claimed in claim 1, wherein the nanorod comprises silicon, germanium, at least one of the III-V semiconductors BN, BP, BAs, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb, at least one of the II-VI semiconductors ZnO, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, BeS, BeSe, BeTe, MgS, MgSe, at least one of the compounds GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, at least one of the compounds CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI;

and/or a metal.

5. The nanoelement field effect transistor as claimed in claim 4, wherein the nanorod is p-doped or n-doped.

6. The nanoelement field effect transistor as claimed in claim 1, wherein the nanotube is a carbon nanotube, a carbon-boron nanotube, a carbon-nitrogen nanotube, a tungsten sulphide nanotube, or a chalcogenide nanotube.

7. The nanoelement field effect transistor as claimed in claim 6, wherein the nanotube is p-doped or n-doped.

8. The nanoelement field effect transistor as claimed in claim 1, wherein the gate-insulating structure covers the entire periphery of the nanoelement, and the gate structure covers the entire periphery of the gate-insulating structure.

9. A nanoelement array, having a plurality of nanoelement field effect transistors as claimed in claim 1.

10. The nanoelement field effect transistor as claimed in claim 1, wherein the nanotube is arranged in a manner such that a flow of electrical charge carriers through the nanotube is substantially parallel to a main processing surface of the substrate.

11. A nanoelement field effect transistor comprising:

a substrate;

a nanoelement on the substrate, the nanoelement being arranged in such a manner on the substrate that a flow of electrical charge carriers through the nanoelement is substantially parallel to a main processing surface of the substrate;

a first source/drain region on and/or in the substrate, the first source/drain region being coupled to a first end portion of the nanoelement;

a second source/drain region on and/or in the substrate, the second source/drain region being coupled to a second end portion of the nanoelement;

a recess in the substrate, the recess arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement;

a gate-insulating structure that covers the of the uncovered periphery of the nanoelement; and

a gate structure that covers the periphery of the gate-insulating structure.

12. The nanoelement field effect transistor as claimed in claim 11, wherein the nanoelement is a nanotube, a bundle of nanotubes, or a nanorod.

13. The nanoelement field effect transistor as claimed in claim 11, wherein the gate-insulating structure comprises silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, and/or hafnium oxide.

14. The nanoelement field effect transistor as claimed in claim 11, wherein the gate structure comprises tantalum nitride, tantalum, molybdenum, nickel, cobalt, titanium nitride, carbon, tungsten, and/or polysilicon.

15. The nanoelement field effect transistor as claimed in claim 11, wherein the nanoelement comprises a nanorod, the nanorod comprising silicon, germanium, at least one of the III-V semiconductors BN, BP, BAs, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb, at least one of the II-VI semiconductors ZnO, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, BeS, BeSe, BeTe, MgS, MgSe, at least one of the compounds GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, at least one of the compounds CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI;

and/or a metal.

16. The nanoelement field effect transistor as claimed in claim 15, wherein the nanorod is p-doped or n-doped.

17. The nanoelement field effect transistor as claimed in claim 11, wherein the nanoelement is a carbon nanotube, a carbon-boron nanotube, a carbon-nitrogen nanotube, a tungsten sulphide nanostructure, or a chalcogenide nanotube.

18. The nanoelement field effect transistor as claimed in claim 17, wherein the nanotube is p-doped or n-doped.

19. A nanoelement array, having a plurality of nanoelement field effect transistors as claimed in claim 11.