METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS

• US 20080296617A1
• Filed: 05/01/2008
• Published: 12/04/2008
• Est. Priority Date: 05/01/2007
• Status: Abandoned Application

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Mishra, Umesh K., McCarthy, Lee S.
• Application Number:
  US12/113,847
• Publication Number:
  US 20080296617A1
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Claims

1. A method for fabricating an electronic device, comprising:

wafer bonding a first semiconductor material to a second semiconductor material, at a temperature below 550°

C., to form a device quality heterojunction between the first semiconductor material and the second semiconductor material, wherein the second semiconductor material is a III-nitride and the first semiconductor material has a different material composition from the second semiconductor material.

2. The method of claim 1, further comprising forming one or more injector regions in the first semiconductor material prior to, or subsequent to, the wafer bonding step, wherein the first semiconductor material is not a III-nitride.

3. The method of claim 2, wherein the first semiconductor material has superior properties for the injector region as compared to the second semiconductor material.

4. The method of claim 3, wherein the superior properties are higher speed of the injector region, higher electron mobility, lower access resistance, or a combination thereof.

5. The method of claim 3, wherein the first semiconductor material has a different lattice constant, thermal properties, and crystalline structure as compared to the second semiconductor material, such that the device quality heterojunction cannot be epitaxially grown.

6. The method of claim 1, wherein the first semiconductor material is Si, SiGe, Si and SiGe, GaP, InP, GaInP or a III-P compound, III-As, or a III-As compound.

7. The method of claim 1, further comprising introducing In, InP, or a III-P or III-As compound on a bonding face of the first semiconductor material or second semiconductor material, prior to the wafer bonding step.

8. A device fabricated using the method of claim 1.

9. The device of claim 8, wherein the device is a heterojunction bipolar transistor or field effect transistor.

10. An electronic device, comprising:

a semiconductor material including one or more injector regions;

a III-nitride material including one or more collector, drain or active regions; and

a device quality heterojunction formed between the semiconductor material and the III-nitride, wherein the semiconductor material is not a III-nitride, the injector regions have one or more superior properties as compared to III-nitride injector regions, and the superior properties include higher speed of the injector region, higher electron mobility, lower access resistance, or a combination thereof.

11. The device of claim 10, further comprising a wafer bond formed between the semiconductor material and the III-nitride to form the device quality heterojunction for reducing thermal mismatch strain, dislocation distribution and impurity distribution in the device.

12. The device of claim 11, further comprising an intermediate region between the semiconductor material and the III-nitride, for enhancing bond strength and conductivity of the device quality heterojunction, wherein the intermediate region is selected from a group comprising In, InP, a III-P or III-As compound, and is on a bonding face of the semiconductor material or III-nitride material.

13. The device of claim 10, wherein the injector regions have reduced dopant diffusion and current leakage as compared to a heterojunction formed at a temperature above 550°

C.

14. The device of claim 10, wherein the injector and collector or drain regions are unipolar.

15. The device of claim 10, wherein the semiconductor material is selected from a group comprising Si, SiGe, or Si and SiGe, III-As or a III-As compound.

16. The device of claim 10, wherein the device is a heterojunction bipolar transistor (HBT) or a field effect transistor (FET).

17. The HBT of claim 16, further comprising:

an emitter region;

a base region between the emitter region and the collector regions;

the collector regions including a first collector layer and a second collector layer, wherein the second collector layer, on the first collector layer, is doped with a same charge carrier type as the first collector layer but with a smaller charge concentration;

the semiconductor material selected from a group comprising Si, SiGe, Si and SiGe, GaP, InP, GaInP or a III-P compound, III-As, or a III-As compound, wherein the semiconductor material includes the injector region and the injector region includes the emitter region and the base region;

the III-nitride including the collector regions, wherein the III-nitride is gallium nitride (GaN); and

a wafer bond formed between the base region of the semiconductor material and the second collector layer of the GaN, thereby forming the device quality heterojunction between the base region and the second collector layer.

18. The FET of claim 16, further comprising:

a source region;

a semiconducting region between the source region and the drain region;

a first drift region between the semiconducting region and the drain region; and

a second drift region between the first drift region and the drain region, wherein;

the semiconductor material is silicon and includes the injector region and the first drift region, and the injector region includes the source region and the semiconducting region;

the III-nitride is gallium nitride (GaN) and includes the second drift region and the drain region;

the first drift region is doped with a same charge carrier type as the drain region, but with a smaller charge concentration than the drain region; and

a wafer bond formed between the first drift region of the semiconducting material and the second drift region of the GaN, thereby forming the device quality heterojunction between the first drift region and the second drift region.

19. An electronic device fabricated using a process comprising:

(a) wafer bonding a first semiconductor material to a second semiconductor material at a temperature below 550°

C. to form a device quality heterojunction between the first semiconductor material and the second semiconductor material;

(b) wherein the first semiconductor material includes one or more injector regions, and the second semiconductor material includes one or more active regions, and

(c) wherein the second semiconductor material comprises a III-nitride semiconductor, the first semiconductor material is different from the second semiconductor material, and the first semiconductor material is selected for superior properties in the injector region as compared to the second semiconductor material.

20. The device of claim 19, wherein the active region is a collector, drain, channel, light emitting region, or light sensitive region.