Semiconductor Devices Including Transistors Having a Recessed Channel Region and Methods of Fabricating the Same

• US 20080296670A1
• Filed: 05/28/2008
• Published: 12/04/2008
• Est. Priority Date: 05/29/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jin-Woo, Han, Sung-Hee, Park, Tai-Su, Lee, Ja-Young, Byun, Hyun-Sook
• Application Number:
  US12/128,190
• Publication Number:
  US 20080296670A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein.

Claims

1. A semiconductor device comprising:

a gate trench in an active region of a semiconductor substrate;

a gate electrode in the gate trench;

a low-concentration impurity region in the active region adjacent to a sidewall of the gate trench; and

a high-concentration impurity region between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench.

2. The semiconductor device of claim 1, wherein the high-concentration impurity region has a higher level than a bottom of the low-concentration impurity region.

3. The semiconductor device of claim 1, wherein the high-concentration impurity region has an impurity concentration gradually reduced downward from a surface of the semiconductor substrate.

4. The semiconductor device of claim 1, wherein the high-concentration and low-concentration regions have bottoms positioned at higher levels than a bottom region of the gate trench.

5. The semiconductor device of claim 1, wherein the gate trench comprises:

an upper gate trench provided in the active region; and

a lower gate trench provided beneath the upper gate trench, the lower gate trench having a greater width than the upper gate trench and a spherical shape.

6. The semiconductor device of claim 1, wherein the gate electrode is buried in the gate trench.

7. The semiconductor device of claim 1, further comprising a contact plug on the high-concentration and low-concentration impurity regions, wherein the contact plug is a doped poly-silicon layer.

8. A method of fabricating a semiconductor device, comprising:

forming a preliminary impurity region in an active region of a semiconductor substrate;

forming a first gate trench through the preliminary impurity region;

forming a high-concentration impurity region in the preliminary impurity region adjacent to a sidewall of the first gate trench, the high-concentration impurity region being formed along the sidewall of the first gate trench;

forming a second gate trench beneath the first gate trench; and

forming a low-concentration impurity region in the preliminary impurity region adjacent to the high-concentration impurity region.

9. The method of claim 8, wherein the low-concentration impurity region is formed to have a lower level than a bottom of the high-concentration impurity region.

10. The method of claim 8, wherein the high-concentration impurity region is formed by selectively implanting impurity ions into the preliminary impurity region through an inner wall surface of the first gate trench.

11. The method of claim 10, wherein the impurity ion implantation is performed using a plasma doping technique or tilt ion implantation technique.

12. The method of claim 8, wherein the forming of the first gate trench comprises sequentially forming a first upper gate trench and a first lower gate trench in the preliminary impurity region, and forming a preliminary high-concentration impurity region in the preliminary impurity region adjacent to a sidewall of the first upper gate trench before forming the first lower gate trench.

13. The method of claim 8, wherein the low-concentration impurity region is formed while forming the high-concentration impurity region or the second gate trench.

14. The method of claim 8, wherein the high-concentration and low-concentration impurity regions have bottoms positioned at higher levels than a bottom region of the second gate trench.

15. The method of claim 8, wherein forming of the first gate trench comprises:

forming a mask pattern for exposing a predetermined region of the preliminary impurity region;

forming a sacrificial spacer on a sidewall of the mask pattern; and

etching the preliminary impurity region exposed by the sacrificial spacer using the mask pattern and the sacrificial spacer as etching masks.

16. The method of claim 15, further comprising implanting impurity ions into the exposed preliminary impurity region such that the preliminary impurity region exposed by the mask pattern has an impurity concentration gradually reduced downward from a surface of the semiconductor substrate before forming the sacrificial spacer.

17. The method of claim 8, wherein the second gate trench is formed to have a greater width than the first gate trench and to have a spherical shape.

18. The method of claim 8, further comprising forming a gate electrode in the first and second gate trenches, wherein the gate electrode is buried in the first gate trench.

19. The method of claim 8, further comprising a contact plug positioned on the high-concentration and low-concentration impurity regions, wherein the contact plug is a doped poly-silicon layer.

20. A method of fabricating a semiconductor device, comprising:

forming a first gate trench in an active region of a semiconductor substrate;

forming a high-concentration impurity region in the active region adjacent to a sidewall of the first gate trench, the high-concentration impurity region being formed along the sidewall of the first gate trench;

forming a second gate trench beneath the first gate trench;

forming a gate electrode in the first and second gate trenches; and

implanting impurity ions into the active region using the gate electrode as an ion implantation mask, thereby forming a low-concentration impurity region adjacent to the high-concentration impurity region.