Double gate manufactured with locos techniques

• US 20080296673A1
• Filed: 05/29/2007
• Published: 12/04/2008
• Est. Priority Date: 05/29/2007
• Status: Abandoned Application

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Tai, Sung-Shan, Hu, Yongzhong
• Application Number:
  US11/807,444
• Publication Number:
  US 20080296673A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a trenched semiconductor power device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with a bottom insulation layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of the bottom insulation attached to sidewalls of the trench extending above a top surface of the bottom trench-filling segment.

Claims

1. A trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein:

said trenched gate further includes at least two mutually insulated trench-filling segments with a bottom insulation layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of said bottom insulation attached to sidewalls of said trench extending above a top surface of said bottom trench-filling segment.

2. The trenched semiconductor power device of claim 1 further comprising:

an inter-segment insulation layer covering a top surface of said bottom trench-filling segment surrounded by said bird-beak shaped layer.

3. The trenched semiconductor power device of claim 1 wherein:

said bottom insulation layer having thickness substantially ranging between 1000 to 3000 Angstroms.

4. The trenched semiconductor power device of claim 1 wherein:

said trenched gate having a bottom portion surrounded by said bottom insulation layer having a slightly smaller width than a top portion of said trenched gate filled with a top trench-filling segment.

5. The trenched semiconductor power device of claim 1 wherein:

said bottom insulation layer comprising a LOCOS oxide layer.

6. The trenched semiconductor power device of claim 1 wherein:

said bottom trench-filling segment comprising a polysilicon doped with phosphorous.

7. The trenched semiconductor power device of claim 1 further comprising:

an inter-segment insulation layer covering a top surface of said bottom trench-filling segment surrounded by said bird-beak shaped layer with a top trench-filling segment comprising a polysilicon disposed on top of said inter-segment insulation layer.

8. The trenched semiconductor power device of claim 2 wherein:

said trenched gate further comprising a top gate insulation layer surrounding sidewalls of a top portion of said gate trench wherein a ratio between a thickness of said top gate insulation layer to a thickness of said inter-segment insulation layer is substantially between 1.2 to 5.

9. The trenched semiconductor power device of claim 1 wherein:

said trenched semiconductor power device constituting a N-channel metal oxide semiconductor field effect transistor (MOSFET) device.

10. The trenched semiconductor power device of claim 1 wherein:

said trenched semiconductor power device constituting a P-channel MOSFET device.

11. The trenched semiconductor power device of claim 1 wherein:

said bottom trench-filling segment constituting an electrode electrically connected to said source region of said MOSFET device.

12. A trenched MOSFET device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein:

said trenched gate further includes at least two mutually insulated trench-filling segments with a bottom oxide layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of said bottom insulation attached to sidewalls of said trench extending above a top surface of said bottom trench-filling segment wherein said bottom insulation layer having thickness substantially ranging between 1000 to 3000 Angstroms;

an inter-segment insulation layer covering a top surface of said bottom trench-filling segment surrounded by said bird-beak shaped layer;

said trenched gate having a bottom portion surrounded by said bottom insulation layer having a slightly smaller width than a top portion of said trenched gate filled with a top trench-filling segment;

said bottom trench-filling segment comprising a polysilicon doped with phosphorous or boron; and

said trenched gate further comprising a top gate insulation layer surrounding sidewalls of a top portion of said gate trench wherein a ratio between a thickness of said top gate insulation layer to a thickness of said inter-segment insulation layer is substantially between 1;

1.2 and 1;

5.

13. The MOSFET device of claim 12 comprising:

a N-channel MOSFET device.

14. The MOSFET device of claim 12 further comprising:

a P-channel MOSFET device.

15. The MOSFET device of claim 12 wherein:

said bottom trench-filling segment constituting an electrode electrically connected to said source region of said MOSFET device.

16. A method for manufacturing a trenched semiconductor power device comprising step of opening a trench in a semiconductor substrate and said method further comprising:

opening a top portion of said trench first then depositing a SiN on sidewalls of said top portion followed by etching a bottom surface of said top portion of said trench then silicon etching to open a bottom portion of said trench with a slightly smaller width than said top portion of said trench.

17. The method of claim 16 further comprising:

growing a thick oxide layer along sidewalls of said bottom portion of said trench thus forming a bird-beak shaped layer at an interface point between said top portion and bottom portion of said trench.

18. The method of claim 17 wherein:

said step of growing said thick oxide layer along sidewalls of said bottom portion of said trench further comprising a step of growing said thick oxide layer substantially having a thickness ranging from 1000 to 3000 Angstroms.

19. The method of claim 17 wherein:

said step of growing said thick oxide layer along sidewalls of said bottom portion of said trench further comprising a step of applying LOCOS process for growing sad thick oxide layer with said bird-beak shaped layer in extending from said bottom portion to said top portion of said trench.

20. The method of claim 17 further comprising:

depositing a polysilicon into said trench followed by doping a N-type dopant followed by etching back said polysilicon to form a bottom trench-filling segment.

21. The method of claim 17 further comprising:

depositing a polysilicon into said trench followed by doping a P-type dopant followed by etching back said polysilicon to form a bottom trench-filling segment.

22. The method of claim 20 further comprising:

growing a gate oxide and an inter-segment insulation layer with a grow rate ration between a silicon and a doped polysilicon up to 1.2 to 5.

23. The method of claim 21 further comprising:

forming a top trench-filling segment by applying a second polysilicon deposition with in-situ doped polysilicon followed by a polysilicon etch-back.

24. The method of claim 22 further comprising:

forming body regions by a body implant and driving-in and forming source regions by a source implant and a source diffusion.