Integrated sensor arrays and method for making and using such arrays

• US 20080296708A1
• Filed: 05/31/2007
• Published: 12/04/2008
• Est. Priority Date: 05/31/2007
• Status: Abandoned Application

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Wodnicki, Robert Gideon, Woychik, Charles Gerard, Durocher, Kevin Matthew, Tian, Wei-Cheng, Fisher, Rayette Ann, Smith, Lowell Scott, Kennerly, Stacey Joy, Wildes, Douglas Glenn
• Application Number:
  US11/809,165
• Publication Number:
  US 20080296708A1
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: G01N 2291/106 one or more transducer arrays
• CPC Class Codes: G01N 29/2406 Electrostatic or capacitive probes, e.g. electret or cMUT-probes
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]

Abstract

The present invention relates to a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon wafer. The method further comprises coupling an SOI wafer to the top surface of the bulk silicon wafer, thinning the back surface of the bulk silicon wafer, coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer, and removing the SOI wafer from the top surface of the bulk silicon wafer.

Claims

1. A method for making an integrated sensor comprising:

providing a sensor array fabricated on or within a top surface of a bulk wafer having a top surface and a bottom surface;

coupling an SOI wafer to the top surface of the bulk silicon wafer;

thinning the back surface of the bulk silicon wafer;

coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer; and

removing the SOI wafer from the top surface of the bulk silicon wafer.

2. The method of claim 1, wherein the bulk wafer is a silicon wafer.

3. The method of claim 1, wherein the integrated sensor comprises a plurality of micromachined ultrasound transducers (MUTs).

4. The method of claim 1 wherein the integrated sensor comprises a plurality of capacitive micromachined ultrasound transducers (cMUTs).

5. The method of claim 1 wherein the integrated sensor comprises a plurality of Piezoelectric micromachined ultrasound transducers (pMUTs).

6. The method of claim 1, wherein the integrated sensor comprises a plurality of photosensors and/or photo-transceivers

7. The method of claim 1, wherein the integrated sensors comprise X-ray sensors.

8. The method of claim 1, wherein the sensor array comprises microelectro-mechanical systems (MEMS) devices

9. The method of claim 8, comprising determining locations of known good MEMS devices in the wafer, and bonding known-good CMOS dies only to the locations of the known good MEMS devices.

10. The method of claim 1, wherein coupling the plurality of integrated circuit die comprises bonding the plurality of integrated circuit die using an epoxy.

11. The method of claim 1, wherein the SOI wafer is removed by etching, grinding, chemical-mechanical polishing (CMP), or a combination thereof

12. The method of claim 1, wherein the SOI wafer is completely removed from the bulk wafer.

13. The method of claim 1, comprising forming vias through the wafer and conformally coating the vias with a conductive material to complete electrical connections to the CMOS dies.

14. The method of claim 1, comprising metallizing an upper surface of the bulk silicon wafer.

15. The method of claim 1, comprising forming a trench through bulk wafer to alleviate stresses within.

16. The method of claim 1, comprising coupling a substrate to the back of the bulk silicon wafer.

17. The method of claim 16, wherein the substrate is further processed or pre-processed to provide integrated active cooling capability.

18. The method of claim 16, wherein the substrate is etched from the back-side in order to create an overall concave structure for the array.

19. The method of claim 16, wherein the array is etched from the front side and the backside substrate is comprised of an acoustic lensing material such that a concave array is realized.

20. The method of claim 16, wherein the substrate is semi-rigid so that the integrated sensor can curve over a surface.

21. The method of claim 16, wherein the substrate is a flexible substrate.

22. The method of claim 16, comprising etching the substrate to form a cavity over which the bulk silicon wafer is fitted.

23. An integrated sensor comprising:

a sensor array disposed on or within a top surface of a bulk silicon wafer having a top surface and a bottom surface;

a plurality of integrated circuit die coupled to the back surface of the bulk silicon wafer.

a plurality of vias disposed between the surface of the bulk silicon wafer and the plurality of integrated circuit die.

24. The integrated sensor of claim 23, wherein the sensor array comprises MEMS devices.

25. The integrated sensor of claim 23, wherein the integrated circuit die comprises a semiconductor die.

26. The integrated sensor of claim 23, comprising an adhesive disposed on the back of the bulk silicon wafer

27. The integrated sensor of claim 23, comprising metalized electrodes disposed on the surface of the bulk silicon wafer and within the vias.

28. A method for making an integrated sensor comprising:

providing a sensor array fabricated on or within a top surface of a bulk silicon wafer having a top surface and a bottom surface;

coupling an SOI wafer to the top surface of the bulk silicon wafer to form a single stack;

thinning the back surface of the stack;

processing the stack; and

removing the SOI wafer from the top surface of the bulk silicon wafer.

29. The method of claim 28, comprising coupling a flexible substrate to the back side of the stack.

30. The method of claim 28, wherein processing the stack comprises micromachining MEMs device cavities within the stack.

31. The method of claim 28, wherein processing the stack comprises disposing semiconductor dies within the stack.