Chip assembly

• US 20080296709A1
• Filed: 05/30/2007
• Published: 12/04/2008
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Nystrom, Michael J., White, Charles
• Granted Patent: US 7,737,513 B2
• Time in Patent Office: Days
• US Class Current: 257/416
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/166 : Material
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip.

Claims

1. An assembly, comprising:

a package element having a top surface;

an integrated circuit chip having a top surface, a bottom surface, and contacts exposed at the top surface, the package element being disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip;

at least one spacer element residing between the top surface of the package element and the bottom surface of the chip, the at least one spacer element forming a substantially closed cavity between the package element and the chip.

2. The assembly of claim 1, further comprising first conductive features extending from the contacts of the chip along the top surface.

3. The assembly of claim 2, wherein the first conductive features further extend along at least one edge surface of the chip.

4. The assembly of claim 3, wherein at least some of the first conductive features extend from the at least one edge surface of the chip to the top surface of the package element.

5. The assembly of claim 2, further comprising a bonding material residing on at least some of the first conductive features.

6. The assembly of claim 2, further comprising second conductive features extending along the package element.

7. The assembly of claim 6, wherein the first and second conductive features are electrically connected.

8. The assembly of claim 6, further comprising an antenna disposed within the cavity, the antenna being electrically connected to the second conductive features.

9. The assembly of claim 6, further comprising elements operable to collectively function as a microelectromechanical system disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

10. The assembly of claim 6, further comprising elements operable to collectively function as a surface acoustic wave device disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

11. The assembly of claim 1, wherein the package element includes silicon.

12. The assembly of claim 1, wherein the package element includes glass.

13. The assembly of claim 1, wherein the chip has a trench extending between the top and bottom surfaces remote from edge surfaces.

14. The assembly of claim 13, further comprising a first conductive feature extending from the contacts of the chip along a surface of the trench.

15. The assembly of claim 13, wherein the trench is formed in a center portion of the integrated circuit.

16. The assembly of claim 13, wherein the trench is rectangular.

17. An assembly, comprising:

a package element having a top surface;

an integrated circuit chip having a top surface, a bottom surface, edge surfaces extending between the top and bottom surfaces and contacts exposed at the top surface, the package element being disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip;

at least one spacer element residing between the top surface of the package element and the bottom surface of the chip, the at least one spacer element forming a cavity between the package element and the integrated circuit chip; and

first conductive features extending from the contacts of the chip along the top surface, at least some of said first conductive features extending along at least one of the edge surfaces of the chip.

18. The assembly of claim 17, wherein the cavity is substantially closed.

19. The assembly of claim 17 wherein at least some of the first conductive features extends from an edge surface of the chip to the top surface of the package element.

20. The assembly of claim 17, further comprising second conductive features extending between the package element and integrated circuit chip into the cavity.

21. The assembly of claim 17, further comprising a bonding material residing on at least some of the first conductive features.

22. The assembly of claim 20, wherein the first conductive features and the second conductive features are connected.

23. The assembly of claim 17, further comprising an antenna disposed within the cavity, the antenna being electrically connected to the second conductive features.

24. The assembly of claim 17, further comprising elements operable to collectively function as a microelectromechanical system disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

25. The assembly of claim 17, further comprising elements operable to collectively function as a surface acoustic wave device disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

26. The assembly of claim 17, wherein the package element includes silicon.

27. The assembly of claim 17, wherein the package element includes glass.

28. The assembly of claim 17, wherein the chip has a trench extending between the top and bottom surfaces remote from the edge surfaces.

29. The assembly of claim 28, wherein at least some of the first conductive features extend along a surface of the trench.

30. The assembly of claim 28, wherein the trench is formed in a center portion of the integrated circuit.

31. The assembly of claim 28, wherein the trench is rectangular.

32. An assembly, comprising:

a package element having a top surface;

an integrated circuit chip having at least one top surface, a bottom surface, contacts exposed at a top surface, and at least one via extending through the chip from a top surface to the bottom surface, the package element being disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip;

at least one spacer element residing between the top surface of the package element and the bottom surface of the chip; and

first conductive features extending from the contacts of the chip along the top surface, at least some of said first conductive features extending through the at least one via of the chip.

33. The assembly of claim 32, wherein the chip includes a main top surface, a lowered top surface, and an edge surface between the main top surface and the lowered top surface, the at least one via extending through the lowered top surface to the bottom surface, and at least some of the first conductive features extending from the contacts along the main top surface, the edge surface, the lowered top surface, and through the via.

34. A method for manufacturing an assembly, comprising:

bonding at least one spacer element between a top surface of a packaging wafer and a bottom surface of a device wafer including integrated circuit chips, so that a top surface of the device wafer having the contacts of the chips faces away from the packaging wafer, and so that the at least one spacer element forms at least one substantially closed cavity between the chip and the wafer; and

severing the wafers around the at least one spacer element.

35. A method as claimed in claim 34 wherein the at least one spacer element includes a plurality of spacer elements and the bonding step is performed so that the plurality of spacer elements define a plurality of substantially enclosed cavities.

36. The method of claim 34, further comprising the step of applying first conductive features extending from the contacts of the chip along the top surface of the chip.

37. The method of claim 36, further comprising the step of applying the first conductive features along at least one edge surface of the chip.

38. The method of claim 37, further comprising applying the first conductive features to extend from an edge surface of the chip to the top surface of the packaging wafer.

39. The method of claim 36, further comprising applying a bonding material to reside on at least some of the first conductive features.

40. The method of claim 36, further comprising applying second conductive features to extend between the packaging wafer and the chip into the cavity.

41. The method of claim 40, further comprising electrically connecting the first conductive features and the second conductive features.

42. The method of claim 34, further comprising forming a trench into each chip so that the trench extends between the top and bottom surfaces of the chip remote from edge surfaces.

43. The method of claim 42, further comprising applying at least some first conductive features so that the extend from the contacts of the chip along a surface of the trench toward the packaging wafer.

44. A method for manufacturing an assembly, comprising:

bonding at least one spacer element between a top surface of a packaging wafer and a bottom surface of a device wafer including integrated circuit chips, so that a top surface of the device wafer having the contacts of the chips faces away from the packaging wafer, and so that the at least one spacer element forms at least one cavity between the chip and the wafer;

severing the wafers around the at least one spacer element; and

applying first conductive features from the contacts of the chip along the top surface of the chip and along at least one edge surface of the chip.

45. The method of claim 44, wherein the at least one spacer element includes a plurality of spacer elements and the bonding step is performed so that the plurality of spacer elements define a plurality of cavities.

46. The method of claim 44, wherein the step of applying the first conductive features is performed so that the first conductive features extend from an edge surface of the chip to the top surface of the packaging wafer.

47. The method of claim 44, further comprising applying a bonding material to reside on at least some of the first conductive features.

48. The method of claim 44, further comprising applying second conductive features to extend between the packaging wafer and the chip into the cavity.

49. The method of claim 48, further comprising electrically connecting the first conductive features and the second conductive features.

50. The method of claim 44, further comprising etching into the chip a trench extending between the top and bottom surfaces remote from edge surfaces.

51. The method of claim 50, further comprising extending some of the first conductive features from the contacts of the chip along a surface of the trench.