Packages and assemblies including lidded chips

• US 20080296717A1
• Filed: 06/01/2007
• Published: 12/04/2008
• Est. Priority Date: 06/01/2007
• Status: Abandoned Application

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Tessera, Inc. (Adeia, Inc.)
• Inventors: Beroz, Masud, Haba, Belgacem, Humpston, Giles, Nystrom, Michael J., Crisp, Richard Dewitt
• Application Number:
  US11/809,780
• Publication Number:
  US 20080296717A1
• Time in Patent Office: Days
• US Class Current: 257/434
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14632 : Wafer-level processed structures
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

A lidded chip is provided which includes a chip having a major surface and a plurality of first chip contacts exposed at the major surface. A lid overlies the major surface. A chip carrier is disposed between the chip and the lid, the chip carrier having an inner surface confronting the major surface and an outer surface confronting the lid. A plurality of first carrier contacts of the chip carrier are conductively connected to the first chip contacts. A plurality of second carrier contacts extend upwardly at least partially through the openings in the lid.

Claims

1. A lidded chip, comprising:

a chip having a major surface and a plurality of first chip contacts exposed at the major surface;

a lid overlying the major surface, the lid having a downwardly facing inner surface, an upwardly facing outer surface, and a plurality of openings extending between the inner and outer surfaces;

a chip carrier having an inner surface confronting the major surface and an outer surface confronting the inner surface of the lid, the chip carrier including a plurality of first carrier contacts conductively connected to the first chip contacts, a plurality of second carrier contacts extending upwardly at least partially through the openings in the lid, and a plurality of traces extending between the first and second carrier contacts.

2. A lidded chip as claimed in claim 1, wherein the chip includes an active region having an optoelectronic device, and the lid is at least partially transmissive to frequencies of interest to the optoelectronic devices.

3. A lidded chip as claimed in claim 2, wherein the chip carrier has an opening permitting transmission of radiation at frequencies of interest between the major surface and a space above the chip carrier.

4. A lidded chip as claimed in claim 3, further comprising a standoff structure supporting an inner surface of the lid from the major surface to define a cavity between the inner and major surfaces.

5. A lidded chip as claimed in claim 1, wherein lateral dimensions of the major surface of the chip are at least substantially the same as lateral dimensions of the lidded packaged chip.

6. A lidded chip as claimed in claim 1, wherein the second carrier contacts include metallic posts such that tips of the posts protrude above the outer surface of the lid.

7. An assembly including the lidded chip as claimed in claim 1, further comprising a circuit panel having terminals conductively joined to the exposed tips of the posts.

8. A lidded chip as claimed in claim 1, wherein the lid has an inner surface bonded to the outer surface of the chip carrier.

9. A lidded chip, comprising:

a chip having a major surface, an active region including an optoelectronic device aligned with the major surface and a plurality of contacts exposed at the major surface;

a lid overlying the active region, the lid having an inner surface confronting the major surface of the chip, an outer surface remote from the inner surface and a plurality of through holes extending between the inner and outer surfaces;

a plurality of conductive package interconnects extending at least partially through the through holes; and

an interconnection element including horizontal metal elements connected to the package interconnects and metal posts connected to the horizontal metal elements, the interconnection element being disposed between the lid and the major surface, the horizontal metal elements extending along the inner surface of the lid, wherein the metal posts interconnect the horizontal metal elements to the contacts on the chip.

10. A lidded chip as claimed in claim 9, wherein the horizontal metal elements include conductive traces.

11. A lidded chip, comprising:

a chip including an active region having an optoelectronic device, the chip having a major surface, edges extending away from the major surface and a plurality of contacts exposed at the major surface;

a lid overlying the chip, the lid having an inner surface confronting the major surface of the chip; and

an interconnection element including a dielectric layer, lands exposed beyond the edges of the chip, conductive traces extending from the lands along the dielectric layer, and metal posts conductively connecting the conductive traces to the contacts on the chip.

12. The lidded chip as claimed in claim 11, further comprising conductive metal bumps extending from the lands away from the inner surface of the lid.

13. A lidded chip, comprising:

a chip having a major surface, an active region including an optoelectronic device at the major surface and a plurality of chip contacts at the major surface;

a lid overlying the active region, the lid having an inner surface confronting the major surface of the chip and an outer surface remote from the inner surface;

a plurality of package interconnects exposed at an exterior surface of the lidded chip;

an interconnection element disposed between the inner surface of the lid and the major surface of the chip, the interconnection element including horizontal metal elements in conductive communication with the contacts and the package interconnects.

14. A lidded chip as claimed in claim 13, wherein the chip includes a plurality of the active regions and the interconnection element includes a plurality of openings aligned with the active regions.

15. A lidded chip as claimed in claim 13, wherein the lid includes through holes extending between the inner and outer surfaces and the package interconnects extend from at least some of the chip contacts at least partially through the through holes.

16. A lidded chip as claimed in claim 13, wherein at least some chip contacts are exposed beyond edges of the lid and the package interconnects include the at least some exposed chip contacts.

17. A lidded chip as claimed in claim 13, wherein at least some chip contacts are exposed within recesses in edges of the lid and the package interconnects include the at least some exposed chip contacts.

18. A lidded chip as claimed in claim 14, wherein the lid includes through holes extending between the inner and outer surfaces and the package interconnects are disposed adjacent to peripheral edges of the chip and extend from at least some of the chip contacts at least partially through the through holes.

19. A lidded microelectronic assembly, comprising:

a microelectronic element having a major surface, a first active region and a second active region at the major surface, first conductive pads conductively connected to the first active region, and second conductive pads conductively connected to the second active region;

a lid overlying the first and second active regions, the lid having an inner surface confronting the major surface, an outer surface remote from the inner surface and a plurality of through holes extending between the inner and outer surfaces;

a plurality of package interconnects extending from the first and second conductive pads at least partially through the through holes; and

an interconnect element overlying the lid including a dielectric element having a first surface confronting the lid, a second surface remote from the first surface, a plurality of first contacts at the first surface joined to the plurality of package interconnects, a plurality of second contacts exposed at the second surface, and a plurality of conductive traces extending along the first surface.

20. A lidded microelectronic assembly as claimed in claim 19, wherein the conductive traces and the package interconnects connect the first conductive pads with the second conductive pads.

21. A lidded microelectronic assembly as claimed in claim 19, wherein the package interconnects include metallic posts extending downwardly from the first surface.

22. A lidded microelectronic assembly as claimed in claim 19, further comprising a second microelectronic element having third contacts, the third contacts conductively connected to the second contacts.

23. A lidded microelectronic assembly as claimed in claim 22, further comprising bond wires, the bond wires conductively connecting the third contacts to the second contacts.

24. A lidded microelectronic assembly as claimed in claim 22, wherein a front face of the second microelectronic element confronts the second surface of the interconnect element, further comprising a fusible metal conductively connecting the second and third contacts.

25. A lidded microelectronic assembly as claimed in claim 19, wherein the first and second active regions include optoelectronic devices and the lid is at least partially transmissive to radiation at frequencies of interest to the optoelectronic devices.

26. A lidded microelectronic assembly as claimed in claim 25, wherein the optoelectronic devices in at least one of the first or second active regions includes an imaging sensor.

27. A lidded microelectronic assembly as claimed in claim 26, further comprising an optical element aligned with at least one of the first or second active regions.

28. A lidded microelectronic assembly as claimed in claim 19, wherein the lid includes openings aligned with the first and second active regions.

29. A lidded microelectronic assembly, comprising:

a microelectronic element having a major surface, a first active region and a second active region at the major surface, first conductive pads conductively connected to the first active region, and second conductive pads conductively connected to the second active region;

at least one lid overlying the first and second active regions, the lid having an inner surface confronting the major surface, an outer surface remote from the inner surface and at least one channel extending between the inner and outer surfaces, the channel exposing the first conductive pads and the second conductive pads;

an interconnect element overlying the lid including a dielectric element having a first surface remote from the lid, a second surface confronting the lid, a plurality of first contacts conductively connected to the first and second conductive pads, a plurality of second contacts, and a plurality of conductive traces extending parallel to the first surface, the conductive traces connecting the first and second contacts.

30. A lidded microelectronic assembly as claimed in claim 29, wherein the first and second contacts are exposed at the first surface, the lidded microelectronic assembly further comprising bond wires, the bond wires conductively connecting the first contacts to the first and second conductive pads.

31. A lidded microelectronic assembly as claimed in claim 29, further comprising locating features protruding downwardly between the second surface of the interconnect element and the outer surface of the lid.

32. A lidded microelectronic assembly as claimed in claim 30, wherein the locating features include metallic posts.

33. A lidded microelectronic assembly as claimed in claim 30, wherein the locating features are bonded to the outer surface of the lid.

34. A lidded microelectronic assembly as claimed in claim 30, wherein the first contacts include conductive features extending downwardly between the second surface and the first and second conductive pads.

35. A lidded microelectronic assembly as claimed in claim 30, wherein the first contacts include metallic posts.

37. A lidded microelectronic assembly as claimed in claim 35, further comprising lid contacts exposed at the outer surface of the lid, conductive traces connecting the lid contacts to the conductive interconnects, and bond wires conductively connecting the second conductive pads to the lid contacts.

39. A lidded microelectronic assembly as claimed in claim 37, further comprising bond wires, the bond wires conductively connecting the first and second conductive pads to the lid contacts.

36. A lidded microelectronic assembly, comprising:

a first microelectronic element having a major surface, an active region at the major surface and first conductive pads exposed at the major surface;

a lid overlying the active region, the lid having an inner surface confronting the major surface, an outer surface remote from the inner surface, a plurality of through holes extending between the inner and outer surfaces, and an opening extending between the inner and outer surfaces;

a plurality of conductive interconnects extending upwardly from the conductive pads at least partially through the through holes; and

a second microelectronic element having a rear face confronting the first microelectronic element within the opening, the second microelectronic element having a front face remote from the rear face and second conductive pads at the front face, the second conductive pads being conductively connected to the conductive interconnects.

38. A lidded microelectronic assembly, comprising:

a first microelectronic element having a major surface, an active region at the major surface and first conductive pads exposed at the major surface;

a lid overlying the active region, the lid having an inner surface confronting the major surface, an outer surface remote from the inner surface and edges extending between the inner and outer surfaces, the lid further including lid contacts exposed at the outer surface, an opening extending between the inner and outer surfaces and a plurality of recesses in at least one edge exposing at least ones of the first conductive pads; and

a second microelectronic element having a rear face confronting the first microelectronic element within the opening, a front face remote from the rear face and second conductive pads at the front face, the first and second conductive pads being conductively connected to the lid contacts.

40. A lidded microelectronic assembly as claimed in claim 38, wherein the lid contacts include first lid contacts and second lid contacts, and the bond wires include first bond wires and second bond wires, wherein the first bond wires conductively connect the first conductive pads to the first lid contacts and the second bond wires conductively connect the second conductive contacts to the second lid contacts, the lidded microelectronic assembly further comprising conductive traces connecting the first lid contacts to the second lid contacts.

42. The method as claimed in claim 40, wherein the step of mounting the lid to chip carrier assembly includes supporting an inner surface of the lid a predetermined distance above the major surface of the chip.

43. The method as claimed in claim 40, wherein the second carrier contacts include metallic posts such that tips of the posts protrude above the outer surface of the lid.

44. The method as claimed in claim 42, wherein the chip carrier includes a dielectric layer defining a major surface, each post of the plurality of posts having a base proximate to the major surface and a tip remote from the base, the base occupying a first area in the plane of the major surface, and the tip occupying a second area in a plane parallel to the major surface, the first area being greater than the second area, and each of the openings occupying a third area greater than the second area and less then the first area, wherein the step of mounting the lid to the chip carrier assembly includes press-fitting the posts into the openings in the lid.

45. The method as claimed in claim 43, further comprising bonding a surface of the chip carrier to an inner surface of the lid with an adhesive.

46. The method as claimed in claim 44, wherein the surface of the chip carrier is bonded to the inner surface of the lid before the chip carrier is assembled together with the chip.

41. A method of fabricating a lidded packaged chip, comprising:

assembling a chip carrier with a semiconductor chip to form a chip carrier assembly such that the chip carrier overlies a major surface of the chip and plurality of first chip contacts of the chip are conductively connected to a plurality of first carrier contacts of the chip carrier, the chip carrier including a plurality of second conductive contacts protruding above a surface of the chip carrier remote from the chip; and

mounting a lid to the chip carrier assembly such that tips of the plurality of second conductive contacts protrude upwardly through openings in the lid and are exposed above an outer surface of the lid remote from the chip carrier.