Cylindrical Bonding Structure and method of manufacture

• US 20080296761A1
• Filed: 06/04/2008
• Published: 12/04/2008
• Est. Priority Date: 01/07/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Chou, Chien-Kang, Lin, Shih-Hsiung, Kuo, Hsi-Shan
• Granted Patent: US 8,890,336 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05672 Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11474 Multilayer masks
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11906 with modification of the same mask
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/1308 : being stacked
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13118 : Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/1312 : Antimony [Sb] as principal constituent
• CPC Class Codes: H01L 2224/13123 : Magnesium [Mg] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.

Claims

1. A chip package comprising:

a substrate comprising a first pad having a top surface with a first region, a second region and a third region between said first and second regions, and a solder mask layer on said first and second regions, wherein an opening in said solder mask layer is over said third region and exposes said third region;

a chip over said substrate, wherein said chip comprises a second pad directly over said first pad;

a copper pillar between said first and second pads;

a tin-containing layer between said copper pillar and said first pad, wherein said tin-containing layer comprises a lower portion in said opening over said third region, and an upper portion on said lower portion, over said opening and above a horizontal level of a top surface of said solder mask layer, wherein said top surface of said solder mask layer faces said chip, and wherein said tin-containing layer has a thickness less than that of said copper pillar and greater than a depth of said opening; and

an underfill between said chip and said substrate.

2. The chip package of claim 1, wherein said tin-containing layer comprises silver.

3. The chip package of claim 1, wherein said copper pillar is electroplated.

4. The chip package of claim 1 further comprising a titanium-containing layer between said copper pillar and said second pad.

5. The chip package of claim 1 further comprising a titanium-tungsten-alloy layer between said copper pillar and said second pad.

6. The chip package of claim 1, wherein said tin-containing layer is directly on said copper pillar.

7. A chip package comprising:

a substrate comprising a first pad having a top surface with a first region, a second region and a third region between said first and second regions, and a solder mask layer on said first and second regions, wherein an opening in said solder mask layer is over said third region and exposes said third region;

a chip over said substrate, wherein said chip comprises a second pad directly over said first pad;

a copper pillar between said first and second pads, wherein said copper pillar has a thickness greater than a depth of said opening, and wherein a shortest distance between said copper pillar and said first pad is greater than said depth of said opening;

a tin-and-gold-containing layer between said copper pillar and said first pad, wherein said tin-and-gold-containing layer has a thickness less than that of said copper pillar; and

an underfill between said chip and said substrate.

8. The chip package of claim 7, wherein said tin-and-gold-containing layer comprises silver.

9. The chip package of claim 7, wherein said tin-and-gold-containing layer comprises copper.

10. The chip package of claim 7, wherein said copper pillar is electroplated.

11. The chip package of claim 7 further comprising a titanium-containing layer between said copper pillar and said second pad.

12. The chip package of claim 7 further comprising a titanium-tungsten-alloy layer between said copper pillar and said second pad.

13. The chip package of claim 7 further comprising a conductive layer between said copper pillar and said tin-and-gold-containing layer.

14. The chip package of claim 7, wherein said tin-and-gold-containing layer is directly on said copper pillar.

15. A chip package comprising:

a substrate comprising a first pad having a top surface with a first region, a second region and a third region between said first and second regions, and a solder mask layer on said first and second regions, wherein an opening in said solder mask layer is over said third region and exposes said third region;

a chip over said substrate, wherein said chip comprises a second pad directly over said first pad;

a copper pillar between said first and second pads;

a tin-containing layer between said copper pillar and said first pad, wherein said tin-containing layer comprises a lower portion in said opening over said third region, and a upper portion on said lower portion, over said opening and above a horizontal level of a top surface of said solder mask layer, wherein said top surface of said solder mask layer faces said chip, and wherein said tin-containing layer has a thickness less than a thickness of said copper pillar and greater than a depth of said opening;

a conductive layer between said copper pillar and said tin-containing layer, wherein said conductive layer has a thickness less than said thickness of said copper pillar; and

an underfill between said chip and said substrate.

16. The chip package of claim 15, wherein said tin-containing layer comprises silver.

17. The chip package of claim 15, wherein said tin-containing layer comprises lead.

18. The chip package of claim 15 further comprising a titanium-containing layer between said copper pillar and said second pad.

19. The chip package of claim 15 further comprising a titanium-tungsten-alloy layer between said copper pillar and said second pad.

20. The chip package of claim 15, wherein said copper pillar is electroplated.

21. A method for fabricating a chip package, comprising:

providing a copper pillar on a chip,

a titanium-containing layer on said pad and on said passivation layer;

a copper pillar on said titanium-containing layer; and

a gold-containing layer over said copper pillar, wherein said gold-containing layer has a thickness less than that of said copper pillar.

between said copper pillar and said first pad, wherein tin-containing layer comprises a lower portion in said opening over said third region, and a upper portion on said lower portion and over said opening, and wherein said tin-containing layer has a thickness less than that of said copper pillar and greater than a depth of said opening; and

an underfill between said chip and said substrate.