Copper nucleation in interconnects having ruthenium layers

• US 20080296768A1
• Filed: 12/14/2006
• Published: 12/04/2008
• Est. Priority Date: 12/14/2006
• Status: Abandoned Application

• Current Assignee: Ramanan V. Chebiam, Valery M. Dubin
• Original Assignee: Ramanan V. Chebiam, Valery M. Dubin
• Inventors: Dubin, Valery M., Chebiam, Ramanan V.
• Application Number:
  US11/639,636
• Publication Number:
  US 20080296768A1
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

A method for fabrication a metal interconnect that includes a ruthenium layer and minimizes void formation comprises forming a barrier layer on a substrate having a trench, depositing a ruthenium layer on the barrier layer, depositing an alloy-seed layer on the ruthenium layer, using an electroless plating process to deposit a copper seed layer on the alloy-seed layer, and using an electroplating process to deposit a bulk metal layer on the copper seed layer. The alloy-seed layer inhibits void formation issues at the ruthenium-copper interface and improves electromigration issues. The electroless copper seed layer inhibits the alloy-seed layer from dissolving into the electroplating bath and reduces electrical resistance across the substrate during the electroplating process.

Claims

1. A method comprising:

depositing a barrier layer on a substrate having a trench;

depositing a ruthenium layer on the barrier layer;

depositing an alloy-seed layer on the ruthenium layer;

using an electroless plating process to deposit a copper seed layer on the alloy-seed layer; and

using an electroplating process to deposit a bulk metal layer on the copper seed layer.

2. The method of claim 1, wherein the barrier layer is deposited using a PVD process.

3. The method of claim 1, wherein the barrier layer comprises at least one of tantalum nitride, titanium nitride, other metal nitrides, or other metals, including but not limited to tantalum, tungsten, tungsten carbide, tungsten nitride, tantalum silicon nitride, titanium nitride, titanium silicon nitride, ruthenium tantalum, tungsten silicon nitride, or ruthenium.

4. The method of claim 1, wherein the ruthenium layer is deposited using one of a PVD process, a CVD process, an ALD process, an electroless plating process, an electroplating process, or a MIP process.

5. The method of claim 1, wherein the alloy-seed layer comprises at least one metal selected from the group consisting of copper, aluminum, tungsten, tantalum, titanium, silver, cobalt, tin, bismuth, nickel, zinc, palladium, platinum, rhenium, ruthenium, gold, boron, berillium, magnesium, manganese, and calcium.

6. The method of claim 1, wherein the alloy-seed layer is deposited using a PVD process, a CVD process, or an ALD process.

7. The method of claim 1, further comprising annealing the copper seed layer prior to using an electroplating process to deposit the bulk metal layer.

8. The method of claim 7, wherein the annealing process takes place at a temperature between around 100°

C. and around 400°

C. for a time period between around 10 seconds and around 1 hour.

9. The method of claim 1, further comprising planarizing the deposited layers to complete fabrication of a metal interconnect.

10. The method of claim 1, wherein the bulk metal layer comprises copper.

11. An apparatus comprising:

a dielectric layer having a trench that is formed on a substrate;

a barrier layer formed on the dielectric layer within the trench;

a ruthenium layer formed in the barrier layer within the trench;

an alloy-seed layer formed on the ruthenium layer within the trench;

an EL copper seed layer formed on the alloy-seed layer within the trench; and

an EP bulk copper layer formed on the EL copper seed layer within the trench.

12. The apparatus of claim 11, wherein the dielectric layer comprises at least one of the following materials:

silicon dioxide, carbon doped oxide, silicon nitride, organic perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass, and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

13. The apparatus of claim 11, wherein the barrier layer comprises at least one of tantalum nitride, titanium nitride, other metal nitrides, or other metals, including but not limited to tantalum, tungsten, tungsten carbide, tungsten nitride, tantalum silicon nitride, titanium nitride, titanium silicon nitride, ruthenium tantalum, tungsten silicon nitride, or ruthenium.

14. The apparatus of claim 11, wherein the barrier layer has a thickness that ranges from 3 Å

to 20 nm.

15. The apparatus of claim 11, wherein the ruthenium layer has a thickness that ranges from 1 nm to 20 nm.

16. The apparatus of claim 11, wherein the alloy-seed layer comprises at least one metal selected from the group consisting of copper, aluminum, tungsten, tantalum, titanium, silver, cobalt, tin, bismuth, nickel, zinc, palladium, platinum, rhenium, ruthenium, gold, boron, berillium, magnesium, manganese, and calcium.

17. The apparatus of claim 11, wherein the alloy-seed layer has a thickness that ranges up to 20 nm.

18. The apparatus of claim 11, wherein the EL copper seed layer has a thickness that ranges from 1 nm to 50 nm.

19. The apparatus of claim 11, wherein the substrate comprises at least on of the following materials:

silicon, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and other Group III-V materials.