Enhanced Output Impedance Compensation

• US 20080297226A1
• Filed: 05/31/2007
• Published: 12/04/2008
• Est. Priority Date: 05/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bhattacharya, Dipankar, Kothandaraman, Makeshwar, Kriz, John C., Morris, Bernard L., Marques, Antonio M.
• Granted Patent: US 7,551,020 B2
• Time in Patent Office: Days
• US Class Current: 327/362
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 5/16 Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Abstract

A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

Claims

1. A compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the compensation circuit comprising:

a first current source operative to generate a first current having a value which is substantially constant;

a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source;

a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and

a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current.

2. The compensation circuit of claim 1, wherein the first current source comprises:

a reference source generating a voltage which is proportional to a supply voltage of the circuit;

a voltage clamp operative to clamp the voltage generated by the reference source across a resistor external to the circuit; and

a current mirror for generating the first current, the first current being a function of a current flowing through the resistor.

3. The compensation circuit of claim 2, wherein the voltage clamp comprises:

an operational amplifier including a first input for receiving the voltage generated by the reference source, a second input for detecting a voltage across the resistor, and an output generating a signal indicative of a difference between the voltage generated by the reference source and the voltage across the resistor; and

an NMOS device configured as a source follower, the NMOS device including a gate connected to the output of the operational amplifier and a source connected to the resistor.

4. The compensation circuit of claim 2, wherein the first current is substantially matched to the current flowing through the resistor.

5. The compensation circuit of claim 2, wherein the first current is a prescribed ratio of the current flowing through the resistor.

6. The compensation circuit of claim 1, wherein the first current source comprises:

a reference source generating a voltage which is proportional to a supply voltage of the compensation circuit;

an operational amplifier having a noninverting input connected to the reference source and an inverting input connected to an external resistor;

an NMOS device having a source connected to the inverting input of the operational amplifier and a gate connected to an output of the operational amplifier; and

a current mirror comprising first and second PMOS devices, a drain of the first PMOS device being connected to a drain of the NMOS device, gates of the first and second PMOS devices being connected to the drain of the NMOS device, sources of the first and second PMOS devices being adapted for connection to the supply voltage of the compensation circuit, and a drain of the second PMOS device generating the first current.

7. The compensation circuit of claim 13 wherein the second current source comprises:

a reference source generating a voltage which is proportional to a supply voltage of the compensation circuit;

a voltage clamp operative to clamp the voltage generated by the reference source across at least a second MOS device, a gate of the at least second MOS device receiving the at least one control signal, the at least second MOS device being substantially matched to the at least first MOS device to be compensated; and

a current mirror circuit operative to generate the second current, the second current being substantially matched to a current flowing through the at least second MOS device.

8. The compensation circuit of claim 7, wherein the current mirror circuit comprises:

a first current mirror operative to source a replicated current which is substantially equal to the current flowing through the at least second MOS device; and

a second current mirror operative to receive the replicated current and to sink the second current, the second current being a function of the replicated current.

9. The compensation circuit of claim 8, wherein the second current is substantially matched to the current flowing through the at least second MOS device.

10. The compensation circuit of claim 8, wherein the second current is a prescribed ratio of the current flowing through the at least second MOS device.

11. The compensation circuit of claim 7, wherein the current mirror circuit comprises:

a first current mirror including first and second PMOS devices, a drain of the first PMOS device being connected to the voltage clamp, gates of the first and second PMOS devices being connected to the drain of the first PMOS device, sources of the first and second PMOS device being adapted for connection to the supply voltage of the compensation circuit, and a drain of the second PMOS device generating a replicated current, the replicated current being substantially equal to the current flowing through the at least second MOS device; and

a second current mirror including first and second NMOS devices, a drain of the first NMOS device being connected to the drain of the second PMOS device, gates of the first and second NMOS devices being connected to the drain of the first NMOS device, sources of the first and second NMOS device being adapted for connection to a voltage return of the compensation circuit, and a drain of the second NMOS device sinking the second current, the second current being substantially equal to the current flowing through the at least second MOS device.

12. The compensation circuit of claim 7, wherein the voltage clamp comprises:

an operational amplifier including a first input for receiving the voltage generated by the reference source, a second input for detecting a voltage across the at least second MOS device, and an output generating a signal indicative of a difference between the voltage generated by the reference source and the voltage across the at least second MOS device; and

an NMOS device configured as a source follower, the NMOS device including a gate connected to the output of the operational amplifier and a source connected to the at least second MOS device.

13. The compensation circuit of claim 1, wherein the processor comprises a digital counter, the counter including a first input for receiving the output signal generated by the comparator and a second input for receiving a timing signal, the counter being operative to generate a digital output code at an output thereof which is indicative of whether the first current is greater in magnitude than the second current.

14. The compensation circuit of claim 1, wherein the processor is operative:

(i) to set the at least one control signal to a logic low level and to check if the output signal generated by the comparator is a low level;

(ii) to set the at least one control signal to a logic high level and to determine if the output signal generated by the comparator is a high level;

(iii) to set the at least one control signal to a midpoint between the low and high levels in steps (i) and (ii) and determine whether the output signal is high, indicating that a desired setting for the at least one control signal lies in a lower half of a range between the low and high levels, or whether the output signal is low, indicating that the desired setting for the at least one control signal lies in an upper half of the range between the low and high levels;

(iv) to set the at least one control signal to a midpoint of the lower or upper half, depending on the comparator output in step (iii); and

(v) repeat steps (iii) and (iv) until consecutive bit states are detected which cannot be divided further.

15. The compensation circuit of claim 1, wherein the at least first MOS device comprises a first plurality of MOS devices to be compensated and the at least second MOS device comprises a second plurality of MOS devices, each MOS device in the second plurality of MOS devices being substantially matched to a corresponding MOS device in the first plurality of MOS devices to be compensated.

16. The compensation circuit of claim 15, wherein the second plurality of MOS devices are formed in close relative proximity to the first plurality of MOS devices, such that the second plurality of MOS devices is subjected to substantially the same variations in process, supply voltage and temperature conditions to which the first plurality of MOS devices are subjected.

17. The compensation circuit of claim 1, wherein the value of the first current is based at least in part on one of a logic low output voltage (Vol) and a logic high output voltage (Voh) specification of the at least first MOS device to be compensated.

18. An integrated circuit including at least one compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the at least one compensation circuit comprising:

a first current source operative to generate a first current having a value which is substantially constant;

a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source;

a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and

a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current.

19. The integrated circuit of claim 18, wherein the processor comprises a digital counter, the counter including a first input for receiving the output signal generated by the comparator and a second input for receiving a timing signal, the counter being operative to generate a digital output code at an output thereof which is indicative of whether the first current is greater in magnitude than the second current.

20. The integrated circuit of claim 18, wherein the processor is operative:

(i) to set the at least one control signal to a logic low level and to check if the output signal generated by the comparator is a low level;

(ii) to set the at least one control signal to a logic high level and to determine if the output signal generated by the comparator is a high level;

(iii) to set the at least one control signal to a midpoint between the low and high levels in steps (i) and (ii) and determine whether the output signal is high, indicating that a desired setting for the at least one control signal lies in a lower half of a range between the low and high levels, or whether the output signal is low, indicating that the desired setting for the at least one control signal lies in an upper half of the range between the low and high levels;

(iv) to set the at least one control signal to a midpoint of the lower or upper half, depending on the comparator output in step (iii); and

(v) repeat steps (iii) and (iv) until consecutive bit states are detected which cannot be divided further.

21. A method for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the method comprising the steps of:

generating a first current having a value which is substantially constant;

generating a second current having a value which is programmable as a function of at least one control signal;

measuring a difference between the respective values of the first and second currents and generating an output signal indicative of relative magnitudes of the first current and the second current;

generating the at least one control signal as a function of the output signal and controlling the value of the second current so that the second current is substantially equal to the first current; and

applying the at least one control signal to the at least first MOS device to thereby compensate the output impedance of the at least first MOS device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected.