CURRENT MIRROR BIAS TRIMMING TECHNIQUE

• US 20080297234A1
• Filed: 05/31/2007
• Published: 12/04/2008
• Est. Priority Date: 05/31/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Pahr, Per Olaf, Martinussen, Tore, Moholt, Jorgen
• Granted Patent: US 7,573,323 B2
• Time in Patent Office: Days
• US Class Current: 327/541
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A reference current is generated by a current mirror circuit. An operational amplifier of a feedback circuit generates a control voltage for control of the feedback circuit transistor. The size of the feedback circuit transistor is trimmed, and the current through the feedback circuit transistor remains relatively constant via operation of the feedback circuit. The feedback circuit transistor is scaled in size relative to the size of current reference transistor(s) (e.g., current sources or sinks), which are tied to the same control voltage. The reference current of the current reference transistors thus varies with the size of the feedback circuit transistor. Further advantageously, transistors providing reference currents for resistor ladders can also be tied to the same control voltage, but scaled proportionally with changes in size to the feedback circuit transistor, thereby maintaining relatively constant voltage from taps of the resistor ladder, even when the feedback circuit transistor is trimmed.

Claims

1. A method of trimming a current reference transistor providing a reference current for an integrated circuit, the method comprising:

using feedback control to generate a control voltage for a gate of a feedback circuit transistor of the integrated circuit such that current passing through the feedback circuit transistor is substantially constant;

using the control voltage for the gate of the feedback circuit transistor to control a gate of the current reference transistor of the integrated circuit, wherein a source of the feedback circuit transistor and a source of the current reference transistor are tied to a same voltage potential; and

adjusting a width-to-length ratio (W/L) of the feedback circuit transistor to trim the reference current flowing through the current reference transistor.

2. The method of claim 1, further comprising determining the current of the current reference transistor and adjusting the width-to-length ratio (W/L) of the feedback circuit transistor at least partially in response to the determined current.

3. The method of claim 1, wherein adjusting further comprises adjusting to trim the reference current flowing through the current reference transistor relative to the current passing through the feedback circuit transistor

4. The method of claim 1, further comprising controlling current for a plurality of current reference transistors, wherein gates of each of the plurality of current reference transistors shares are operatively coupled to the same voltage as the gate of the feedback circuit transistor, and wherein sources of each of the plurality of current reference transistors are operatively coupled to the source of the feedback circuit transistor.

5. The method of claim 1, wherein using the control voltage comprises the feedback circuit transistor and the at least one current reference transistor are PMOS.

6. The method of claim 1, wherein the feedback circuit transistor and the at least one current reference transistor are NMOS.

7. The method of claim 1, wherein using feedback control comprises further comprising using an operational amplifier for the feedback control.

8. The method of claim 1, wherein using feedback control comprises:

providing the current passing through the feedback circuit transistor to a feedback circuit resistor, wherein the feedback circuit resistor is integrated into the integrated circuit;

providing a voltage generated by the current passing through the feedback circuit resistor as a feedback signal for a first input to an operational amplifier of the integrated circuit;

providing a voltage reference as a second input to the operational amplifier; and

coupling an output of the operational amplifier to the gate of the feedback circuit transistor for control of the gate voltage.

9. The method of claim 8, further comprising adjusting to trim the reference current flowing through the current reference transistor relative to the current passing through the feedback circuit transistor.

10. The method of claim 1, further comprising operatively coupling the current reference to a current reference input of a digital-to-analog converter, wherein the digital-to-analog converter is integrated in the integrated circuit.

11. The method of claim 1, wherein adjusting the width-to-length ratio (W/L) comprises selectively activating multiple fingers of the feedback circuit transistor.

12. The method of claim 11, wherein adjusting the width-to-length ratio (W/L) is performed during production test, and permanently setting the adjustment into the integrated circuit.

13. The method of claim 1, further comprising:

controlling current for a voltage reference transistor, wherein the voltage reference transistor is integrated with the integrated circuit;

adjusting a width-to-length ratio (W/L) of the voltage reference transistor proportionally with the width-to-length ratio (W/L) of the feedback circuit transistor;

providing the current passing through the voltage reference transistor to a resistor ladder, wherein the resistor ladder is integrated with the integrated circuit; and

using one or more taps of the resistor ladder as voltage references.

14. The method of claim 13, wherein adjusting the width-to-length ratio (W/L) of the feedback circuit transistor and the voltage reference transistor comprises selectively activating multiple fingers of the feedback and voltage reference transistors such that a scale between the transistors remains approximately the same.

15. The method of claim 13, further comprising trimming a resistor of the resistor ladder to adjust the voltage references.

16. An integrated circuit comprising:

a current reference transistor having a gate, a source, and a drain;

a feedback circuit transistor having a gate, a source, and a drain, wherein the gate of the feedback circuit transistor is operatively coupled to the gate of the current reference transistor, wherein the source of the feedback circuit transistor is operatively coupled to the source of the current reference transistor, wherein a number of activated fingers of the feedback circuit transistor is selectable such that a width-to-length ratio (W/L) of the feedback circuit transistor is scalable; and

a feedback circuit configured to generate a control voltage for the gate of the feedback circuit transistor, wherein the feedback circuit is configured to maintain a substantially constant current through the feedback circuit transistor.

17. The integrated circuit of claim 16, wherein the feedback circuit comprises:

an operational amplifier; and

a feedback circuit resistor with a terminal operatively coupled to a drain of the feedback circuit transistor and to a first input of the operational amplifier.

18. The integrated circuit of claim 17, wherein the feedback circuit comprises a voltage reference operatively coupled to a second input of the operational amplifier.

19. The integrated circuit of claim 16, wherein the feedback circuit transistor is scalable relative to the current reference transistor.

20. The integrated circuit of claim 16, further comprising a digital to analog converter operatively coupled to the current reference transistor.

21. The integrated circuit of claim 16, further comprising:

a voltage reference transistor having a gate, a source, and a drain, wherein the gate of the voltage reference transistor is operatively coupled to the gate of the feedback circuit transistor, wherein the source of the voltage reference transistor is operatively coupled to the source of the feedback circuit transistor, wherein a number of activated fingers of the voltage reference transistor is selectable and configured during test such that a width-to-length ratio (W/L) of the voltage reference transistor is scaled proportionally with the width-to-length ratio (W/L) of the feedback circuit transistor; and

a resistor ladder operatively coupled to a drain of the voltage reference transistor, wherein a tap of the resistor ladder provides a voltage reference.

22. The integrated circuit of claim 21, wherein the feedback circuit transistor is scalable relative to the current reference transistor.

23. The integrated circuit of claim 16, wherein the current reference transistor and the feedback circuit transistor comprise PMOS.

24. The integrated circuit of claim 16, wherein the current reference transistor and the feedback circuit transistor comprise NMOS.

25. An apparatus for trimming an integrated circuit, the apparatus comprising:

a current monitoring circuit configured to monitor a current of a first transistor of the integrated circuit; and

a selection circuit configured to select a number of fingers of a second transistor to adjust a current flowing through the first transistor.

26. The apparatus of claim 25, wherein the current monitoring circuit is configured to aggregate current from a plurality of current reference transistors of the integrated circuit.

27. The apparatus of claim 25, wherein the selection circuit is further configured to permanently select the number of fingers for the integrated circuit.

28. The apparatus of claim 25, further comprising a resistor trimming apparatus configured to trim a resistor of a resistor ladder, wherein the resistor ladder provides one or more voltage references, wherein a current flowing through the resistor ladder from a third transistor partially determines the voltage of the voltage references, and wherein the selection circuit is configured to select a number of fingers of the third transistor such that a width-to-length ratio of the third transistor scales proportionally with a width-to-length of the first transistor.

29. A method of configuring a current reference of an integrated circuit, the method comprising:

monitoring a current of a first transistor of the integrated circuit; and

selecting a number of fingers of a second transistor to adjust a current flowing through the first transistor.

30. The method of claim 29, wherein monitoring further comprising aggregating current from a plurality of current reference transistors of the integrated circuit for monitoring of current.

31. The method of claim 29, wherein selecting further comprising permanently selecting the number of fingers for the integrated circuit.

32. The method of claim 29, further comprising:

trimming a resistor of a resistor ladder, wherein the resistor ladder provides one or more voltage references, wherein a current flowing through the resistor ladder from a third transistor partially determines the voltage of the voltage references; and

selecting a number of fingers for the third transistor such that a width-to-length ratio of the third transistor scales proportionally with a width-to-length ratio of the first transistor.