ULTRA-WIDEBAND VARIABLE-PHASE RING-OSCILLATOR ARRAYS, ARCHITECTURES, AND RELATED METHODS

• US 20080297414A1
• Filed: 06/02/2008
• Published: 12/04/2008
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: University of Southern California
• Original Assignee: University of Southern California
• Inventors: Krishnaswamy, Harish, Hashemi, Hossein
• Granted Patent: US 7,848,719 B2
• Time in Patent Office: Days
• US Class Current: 342/368
• CPC Class Codes: H01Q 3/28 varying the amplitude
• CPC Class Codes: H01Q 3/36 with variable phase-shifters
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

Variable phase ring oscillators are described that provide a linear phase progression between adjacent elements in an antenna array by providing a symmetric ring configuration of tuned amplifiers and a single phase shifter. The ring topology is coupled to a single PLL that allows for direct modulation and demodulation of arbitrary waveforms without using RF up/down converting mixers. The PLL distributes the transmit waveforms to all antenna elements in the transmit mode and combines the received waveforms in the receive mode without any complicated power distribution network. Ultra-wideband architectures and methods are described that utilize a first reference signal source, a VPRO, and a second reference signal source. Related methods are controlling an array and beam steering are also described.

Claims

1. An ultra-wideband variable-phase ring-oscillator circuit comprising:

a plurality of tuned amplifiers configured in series as a ring, wherein the ring includes a plurality of output nodes for connection to a plurality of antennas;

a first phase-locked loop connected to the ring, wherein the first-phased locked loop includes a first phase shifter coupled to the ring, wherein the first phase shifter provides a phase delay between each pair of successive tuned amplifiers; and

a reference oscillator configured and arranged to produce an output and connected to the first phase-locked loop by a reference path, wherein the reference oscillator is locked to a reference frequency source by a second phase-locked loop having a plurality of static frequency dividers producing a division factor; and

a plurality of squarers, each connected to a respective output node, and configured and arranged to double the operational frequency of a signal provided by the ring.

2. The circuit of claim 1, further comprising a plurality of power amplifiers, each connected to a respective frequency squarer.

3. The circuit of claim 2, wherein each power amplifier comprises 2-bit binary-weighted switched capacitors.

4. The circuit of claim 3, wherein each power amplifier further comprises two differential pairs.

5. The circuit of claim 4, wherein each power amplifier is configured as a cascode pair.

6. The circuit of claim 1, wherein the reference oscillator is operational at about 12 GHz.

7. The circuit of claim 1, wherein the second phase-locked loop includes a frequency divider providing a division ratio of 128.

8. The circuit of claim 1, further comprising a plurality of antennas coupled to the plurality of output nodes of the tuned amplifiers, wherein the plurality of antennas are configured and arranged as an array.

9. The circuit of claim 8, wherein the plurality of tunable amplifiers and first phase-locked loop are disposed on a semiconductor substrate.

10. The circuit of claim 9, wherein the second phase-locked loop is disposed on the semiconductor substrate.

11. The circuit of claim 9, wherein the plurality of antennas are disposed on the semiconductor substrate.

12. The circuit of claim 1, wherein the plurality of tuned amplifiers are configured in a two dimensional m×

n array.

13. The circuit of claim 12, further comprising m first phase shifters, each coupled to a separate ring in the m dimension of the m×

n array and n second phase shifters, each coupled to a separate ring in the m×

n array.

14. The circuit of claim 8, wherein the antenna array is operational at about 24 GHz to about 27 GHz.

15. A method of providing steerable control of an antenna array, the method comprising:

setting a phase distribution between adjacent tuned amplifiers of a variable phase ring oscillator that is connected to an antenna array by multiple output nodes;

connecting the ring oscillator to a first reference source;

connecting the first reference source to a second reference source by a first phase-locked loop providing a division factor;

generating in-phase and quadrature components of the first reference source;

mixing the in-phase and quadrature components of the first reference source with baseband in-phase and quadrature inputs;

providing a modulated ultra-wideband reference signal to the variable phase ring oscillator through a second phase-locked loop; and

providing beam steering for the antenna array by outputs from the variable phase ring oscillator.

16. The method claim 15, further comprising determining relative direction from an automobile connected to the antenna array to an object separate from the automobile.

17. The method of claim 15, further comprising doubling the frequency provided at the output nodes.

18. The method of claim 17, wherein doubling the frequency comprises using a squarer including a self-mixer.

19. The method of claim 15, wherein the first reference source provides a reference signal of about 12 GHz.

20. The method of claim 15, further comprising using varactors for frequency control of the tuned amplifiers of the variable phase ring oscillator.

21. The method of claim 20, further comprising using the frequency control for beam steering of the antenna array with 2-bit resolution.

22. The method of claim 15, further comprising using sign inversion for beam steering resolution of the antenna array.

23. The method of claim 22, wherein using sign inversion comprises using two differential pairs with inverted inputs.

24. The method of claim 15, further comprising operating the antenna array at about 24 GHz to about 27 GHz.