Display device

• US 20080297449A1
• Filed: 03/10/2008
• Published: 12/04/2008
• Est. Priority Date: 03/16/2007
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Uchino, Katsuhide, Yamashita, Junichi
• Application Number:
  US12/075,215
• Publication Number:
  US 20080297449A1
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage-capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage-capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction; and with the control unit, buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line are arrayed in a column in the longitudinal direction of the laser beam irradiation.

Claims

1. A display device comprising:

a pixel array unit where pixel circuits are disposed in a matrix form, said pixel circuit including

a driving transistor configured to generate a driving current,

an electro-optic element connected to the output terminal side of said driving transistor,

a storage-capacitor for storing information corresponding to the signal potential within a picture signal supplied via a picture signal line, and

a sampling transistor configured to write information corresponding to said signal potential in said storage-capacitor, with said electro-optic element emitting light by generating a driving current based on information stored in said storage-capacitor at said driving transistor to be applied to said electro-optic element; and

a control unit, of which the output stage includes a buffer transistor, configured to output a pulse signal for driving said pixel array unit from said buffer transistor;

wherein said pixel array unit and said control unit are formed with long laser beam irradiation with a predetermined wavelength to be scanned in the vertical direction;

and wherein with said control unit, of said buffer transistors, buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line are arrayed in a column in the longitudinal direction of said laser beam irradiation.

2. The display device according to claim 1, wherein with said control unit, of said buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line, a buffer transistor for determining the start timing of a certain operation to be realized by driving said pixel circuit, and a buffer transistor for determining the end timing thereof are disposed by being arrayed in a column in the longitudinal direction of said laser beam irradiation.

3. The display device according to claim 2, wherein a buffer transistor for determining said start timing and a buffer transistor for determining said end timing are each configured as an inverter-type buffer where a p-type transistor and an n-type transistor are cascade-connected;

and wherein of the respective p-type transistor and n-type transistor pairs, one for determining said start timing, and the other for determining said end timing, are disposed by being arrayed in a column in the longitudinal direction of said laser beam irradiation.

4. The display device according to claim 2, wherein a buffer transistor for determining said start timing and a buffer transistor for determining said end timing are each configured as an inverter-type buffer where a p-type transistor and an n-type transistor are cascade-connected;

and wherein all of the respective p-type transistor and n-type transistor pairs are disposed by being arrayed in a column in the longitudinal direction of said laser beam irradiation.

5. The display device according to claim 2, wherein at least one of a buffer transistor for determining said start timing and a buffer transistor for determining said end timing is an analog switch having a transfer gate configuration where two switching transistors having a different polarity are combined, and the remaining one is configured as an inverter-type buffer where a p-type transistor and an n-type transistor are cascade-connected;

and wherein two switching transistors making up said analog switch for determining said start timing or said end timing, and one of a p-type transistor and an n-type transistor for determining the remaining one of said start timing and said end timing, are disposed by being arrayed in a column in the longitudinal direction of said laser beam irradiation.

6. The display device according to claim 3, wherein said start timing and said end timing are determined with on/off timing of two types of driving pulse.

7. The display device according to claim 3, wherein said start timing and said end timing are determined with on/off timing of a single driving pulse.

8. The display device according to claim 1, wherein said pixel array unit includes said driving transistor or a driving current fluctuation suppressing unit for suppressing fluctuation of said driving current along with the property fluctuation of said electro-optic element;

and wherein said control unit includes

a write scanning unit for sequentially scanning said pixel circuits by sequentially controlling said sampling transistor in a horizontal cycle, and outputting a write scanning pulse for writing information corresponding to the signal potential of a picture signal in one row worth of each storage-capacitor from said buffer transistor, and

a correction scanning unit for outputting a correction pulse for controlling said driving current fluctuation suppressing unit from said buffer transistor;

and wherein with at least one of said write scanning unit or said correction scanning unit, of said buffer transistors, a buffer transistor for determining the start timing of an operation for suppressing fluctuation of said driving current,

and a buffer transistor for determining the end timing thereof are disposed by being arrayed in a column in the longitudinal direction of said laser beam irradiation.

9. The display device according to claim 8, wherein said driving current fluctuation suppressing unit is configured to perform mobility correction for adding correction worth as to the mobility of said driving transistor to information to be written in said storage-capacitor;

and wherein of said buffer transistors, a buffer transistor for determining the start timing of said mobility correction, and a buffer transistor for determining the end timing thereof are disposed by being arrayed in a column in the longitudinal direction of said laser beam irradiation.