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INTELLIGENT DEAD TIME CONTROL

  • US 20080298101A1
  • Filed: 06/01/2007
  • Published: 12/04/2008
  • Est. Priority Date: 06/01/2007
  • Status: Active Grant
First Claim
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1. A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high side control transistor and a low side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node, the circuit comprising:

  • a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and

    a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage.

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