FOUR POLE NEUTRAL-POINT CLAMPED THREE PHASE CONVERTER WITH LOW COMMON MODE VOLTAGE OUTPUT

• US 20080298103A1
• Filed: 06/02/2008
• Published: 12/04/2008
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: DRS Naval Power Systems, Inc. (Leonardo S.p.A.)
• Original Assignee: DRS Power & Control Technologies, Inc. (Finmeccanica SPA)
• Inventors: Bendre, Ashish R., Goshaw, Craig, Cuzner, Robert M., Vander Meer, James C.
• Granted Patent: US 7,920,393 B2
• Time in Patent Office: Days
• US Class Current: 363/89
• CPC Class Codes: H02M 1/123 Suppression of common mode voltage or current
• CPC Class Codes: H02M 1/385 with means for correcting output voltage deviations introduced by the dead time
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters

Abstract

A four pole, three-phase, NPC converter that produces virtually no common mode voltage. The low common mode voltage output is achieved by constraining the switch states of the NPC converter. A fourth pole and associated control balance the upper and lower DC link voltages. The converter may be an inverter or a rectifier.

Claims

1. A three-level neutral point clamped converter comprising:

a first pole;

a second pole;

a third pole;

a fourth pole,

each of the first, second, and third poles having a first switch, a second switch, a third switch, and a fourth switch coupled in series between a positive DC bus and a negative DC bus,

the fourth pole having a first switch and a second switch coupled in series between the positive DC bus and the negative DC bus,

an AC bus being connected between the second switch and the third switch of the first, second, and third poles,

a neutral line being connected through a diode between the first switch and the second switch and between the third switch and the fourth switch of the first, second, and third poles,

the first and second switches defining an upper portion, the third and fourth switches defining a lower portion; and

a controller that

switches states of the respective first, second, third, and fourth switches of the first, second, and third poles to produce zero common mode voltage, the fourth pole enabling all of the NPC switch states of the first, second, and third poles to be used for producing zero common mode voltage, and

modulates the first and second switches of the fourth pole to balance the positive DC bus and the negative DC bus.

2. The three-level neutral point clamped converter of claim 1, wherein the converter is an inverter.

3. The three-level neutral point clamped converter of claim 1, wherein the converter is a rectifier.

4. The three-level neutral point clamped converter of claim 1, wherein the controller compensates for the effects of dead time by delaying commutation of a respective one of the first, second, and third poles.

5. The three-level neutral point clamped converter of claim 1, wherein the controller effects production of zero common mode voltage by implementing a two-level modulation scheme and mapping two-level states to three-level states.

6. The three-level neutral point clamped converter of claim 5, wherein the two-level modulation scheme is space vector modulation.

7. The three-level neutral point clamped converter of claim 1, wherein the controller balances the positive DC bus and the negative DC bus by measuring the difference between upper and lower DC link voltages, and commanding either the upper portion or the lower portion of a respective pole to turn on depending on whether charge must be pulled out of the upper portion'"'"'s DC link or out of the lower portion'"'"'s DC link to maintain the balance.

8. The three-level neutral point clamped converter of claim 1, wherein the first switch of the first pole includes the first switch and a third switch and the second switch of the fourth pole includes the second switch and a fourth switch, and the neutral line is connected between the third switch and the second switch of the fourth pole through an inductance.

9. A method for controlling a three-level neutral point clamped converter having a first pole, a second pole, a third pole, and a fourth pole, each of the first, second, and third poles having a first switch, a second switch, a third switch, and a fourth switch coupled in series between a positive DC bus and a negative DC bus, the fourth pole having a first switch and a second switch coupled in series between the positive DC bus and the negative DC bus, an AC bus being connected between the second switch and the third switch of the first, second, and third poles, a neutral line being connected through a diode between the first switch and the second switch and between the third switch and the fourth switch of the first, second, and third poles, the first and second switches defining an upper portion, the third and fourth switches defining a lower portion, the method comprising the steps of:

switching states of the respective first, second, third, and fourth switches of the first, second, and third poles to produce zero common mode voltage, the fourth pole enabling all of the NPC switch states of the first, second, and third poles to be used for producing zero common mode voltage; and

modulating the first and second switches of the fourth pole to balance the positive DC bus and the negative DC bus.

10. The method of claim 9, wherein the converter is an inverter.

11. The method of claim 9, wherein the converter is a rectifier.

12. The method of claim 9, further comprising the step of:

compensating for the effects of dead time by delaying commutation of a respective one of the first, second, and third poles.

13. The method of claim 9, wherein switching states to produce zero common mode voltage includes implementing a two-level modulation scheme and mapping two-level states to three-level states.

14. The method of claim 13, wherein the two-level modulation scheme is space vector modulation.

15. The method of claim 9, wherein modulating the first, second, third, and fourth switches of the fourth pole to balance the positive DC bus and the negative DC bus includes measuring the difference between upper and lower DC link voltages, and commanding either the upper portion or the lower portion of a respective pole to turn on depending on whether charge must be pulled out of the upper portion'"'"'s DC link or out of the lower portion'"'"'s DC link to maintain the balance.

16. The method of claim 9, wherein the first switch of the first pole includes the first switch and a third switch and the second switch of the fourth pole includes the second switch and a fourth switch, and the neutral line is connected between the third switch and the second switch of the fourth pole through an inductance.