Resistive memory architectures with multiple memory cells per access device

• US 20080298113A1
• Filed: 05/31/2007
• Published: 12/04/2008
• Est. Priority Date: 05/31/2007
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Violette, Mike, Liu, Jun
• Granted Patent: US 7,684,227 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Claims

1. A resistive memory structure, comprising:

an access device;

at least two resistive memory cells, each cell coupled to the access device and to a cell select signal line and each configured to pass current when selected via a cell select signal on a said line and upon activation of the access device; and

at least two rectifying devices, each connected with a respective one of the at least two memory cells.

2. The structure of claim 1, wherein the rectifying devices prevent parallel leak currents between a selected memory cell and non-selected memory cells.

3. The structure of claim 1, wherein the rectifying devices are coupled between the memory cells and the access device.

4. The structure of claim 3, wherein the memory cells are each coupled to respective cell select lines.

5. The structure of claim 3, wherein the memory cells are in a single plane above the access device.

6. The structure of claim 3, wherein the rectifying devices are formed at least partially within the access devices.

7. The structure of claim 6, wherein the rectifying devices are p-n diodes.

8. The structure of claim 6, wherein the rectifying devices are Schottky diodes.

9. The structure of claim 3, wherein the memory cells are stacked in pairs with memory cells from other adjacent memory structures.

10. The structure of claim 9, wherein the stacked pairs of memory cells share a common electrode.

11. The structure of claim 10, wherein the stacked pairs of memory cells are coupled to the cell select line via the common electrode.

12. The structure of claim 9, wherein the structure is organized in a staggered arrangement with the other adjacent memory structures.

13. The structure of claim 12, wherein the other adjacent memory structures are organized above respective access devices.

14. The structure of claim 9, wherein the structure is organized in a parallel arrangement with the other adjacent memory structures.

15. The structure of claim 14, wherein the other adjacent memory structures are organized above shared access devices.

16. The structure of claim 1, wherein the memory cells are coupled between the rectifying devices and the access device.

17. The structure of claim 16, wherein the memory cells are each coupled to respective cell select lines.

18. The structure of claim 17, wherein each memory cell shares a rectifying device with at least one other memory cell, and wherein the memory cells sharing the same rectifying device are each coupled to a different access device.

19. The structure of claim 17, wherein the memory cells are stacked in pairs with memory cells from other adjacent memory structures.

20. The structure of claim 17, wherein four memory cells share the same rectifying device.

21. The structure of claim 20, wherein the different access devices are organized in a parallel arrangement.

22. The structure of claim 1, wherein the rectifying devices are selected from a group comprising of p-n junction diodes and Schottky diodes.

23. The structure of claim 1, wherein the rectifying devices are formed within the access device.

24. The structure of claim 1, wherein the memory cells are arranged vertically with respect to the access device and each other.

25. The structure of claim 1, wherein the memory cells are in a single plane above the access device.

26. The structure of claim 1, wherein the memory cells are phase change memory cells.

27. A phase change memory device, comprising:

an array of access devices;

at least two phase change memory cells coupled to each access device, each cell being configured to pass current when selected via a cell select signal from a coupled cell select line and upon activation of an associated coupled access device; and

a rectifying device connected to each memory cell, each being configured to prevent parallel leak currents between a selected memory cell and non-selected memory cells.

28. The device of claim 27, wherein the rectifying device for each cell is coupled between the memory cell and the access device.

29. The device of claim 28, wherein the memory cells are each coupled to respective cell select lines.

30. The device of claim 28, wherein the rectifying device for each cell is within the respective access device.

31. The device of claim 30, wherein the rectifying device for each cell is selected from a group comprising a p-n junction diode and a Schottky diode.

32. The device of claim 28, wherein the memory cells are in a single plane above the array of access devices.

33. The device of claim 27, wherein each memory cell is coupled between the corresponding access device and rectifying device.

34. The device of claim 33, wherein each memory cell shares a rectifying device with at least one other memory cell, and wherein the memory cells sharing the same rectifying device are each coupled to a different access device.

35. The device of claim 34, wherein four memory cells share the same rectifying device.

36. The device of claim 34, wherein the memory cells sharing the same rectifying device are stacked in pairs comprising a lower memory cell and an inverted upper memory cell.

37. The device of claim 36, wherein for each stacked pair, the lower memory cell and the upper memory cell share a first electrode coupled to the shared rectifying device.

38. The device of claim 36, wherein two stacked pairs of memory cells share a first electrode coupled to the shared rectifying device.

39. The device of claim 36, wherein the memory cells coupled to the same access device are positioned above different access devices.

40. The device of claim 36, wherein the access devices are arranged as a staggered array.

41. The device of claim 36, wherein the access devices are arranged as a parallel array.

42. The device of claim 33, wherein the rectifying devices are selected from a group comprising p-n junction diodes and Schottky diodes.

43. The device of claim 27, wherein the memory cells are arranged vertically with respect to the access device and each other.

44. The device of claim 43, wherein at least two memory cells are coupled to each access device.

45. The device of claim 43, wherein each memory cell is coupled between the corresponding access device and rectifying device.

46. A phase change memory device, comprising:

an array of access devices;

a first and a second phase change memory cell coupled to each access device, each cell being configured to pass current when selected via a cell select signal from a coupled cell select line and upon activation of an associated coupled access device, the first cell being a lower cell of a first pair of stacked memory cells, the second cell being an upper cell of a second pair of stacked memory cells; and

a rectifying device connected to each memory cell, each being configured to prevent parallel leak currents between a selected memory cell and non-selected memory cells.

47. The device of claim 46, wherein the first pair is positioned above the access device and the second pair is positioned above a different access device.

48. The device of claim 46, wherein two stacked memory cell pairs are positioned above the access device, including the first pair but not including the second pair.

49. The device of claim 46, wherein the first pair and the second pair are positioned above access devices that are activated by a same word line.

50. The device of claim 46, wherein the first pair and the second pair are positioned above access devices that are activated by different word lines.

51. A processing system, comprising:

a processor;

a resistive memory coupled to the processor, the resistive memory comprising;

at least one array of access devices;

at least two resistive memory cells coupled to each access device, each cell being configured to pass current when selected via a cell select signal and upon activation of an associated coupled access device; and

a rectifying device connected to each memory cell, each being configured to prevent parallel leak currents between a selected memory cell and non-selected memory cells.

52. The system of claim 51, wherein the rectifying device for each cell is coupled between the memory cell and the associated access device.

53. The system of claim 51, wherein each memory cell is coupled between the corresponding access device and rectifying device.

54. The system of claim 53, wherein each memory cell shares a rectifying device with at least one other memory cell, and wherein the memory cells sharing the same rectifying device are each coupled to a different access device.

55. The system of claim 51, wherein each memory cell is stacked with at least one other memory cell.

56. The system of claim 55, wherein each stacked pair of memory cells shares a common rectifying device.

57. The system of claim 55, wherein each stacked pair of memory cells shares a common electrode.

58. A method of fabricating a resistive memory structure, the method comprising:

forming an access device with a source, drain and gate, the source and drain being doped to a first dopant type;

depositing inter-level dielectrics on top of the access device;

etching a via through the inter-level dielectrics to either the doped source or drain;

doping a bottom of the via with a second dopant type to form a rectifying device at the bottom of the via;

filling the via; and

forming a resistive memory cell above the via so that the cell is electrically coupled to the access device through the via and the rectifying device.

59. The method of claim 58, wherein more than one rectifying device is formed within the source or drain of the access device.

60. The method of claim 59, wherein doping the bottom of each via results in a doped region shared by more than one via.

61. The method of claim 58, wherein the rectifying device formed is either a p-n junction diode or a Schottky diode.