CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEVICES

• US 20080298142A1
• Filed: 05/31/2007
• Published: 12/04/2008
• Est. Priority Date: 05/31/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Jung, Chang Ho, Chen, Zhiqin
• Granted Patent: US 7,881,147 B2
• Time in Patent Office: Days
• US Class Current: 365/194
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.

Claims

1. An integrated circuit comprising:

a first clock generator configured to generate a first clock signal used for read and write operations; and

a second clock generator configured to generate a second clock signal used for write operations.

2. The integrated circuit of claim 1, wherein the first clock generator comprises

a first circuit configured to generate leading edges on the first clock signal based on an external clock signal and to generate trailing edges on the first clock signal based on a reset signal.

3. The integrated circuit of claim 2, wherein the first clock generator further comprises

a second circuit configured to maintain logic level of the first clock signal between the leading and trailing edges triggered by the external clock signal and the reset signal.

4. The integrated circuit of claim 1, wherein the second clock generator is disabled for read operations.

5. The integrated circuit of claim 1, wherein the first and second clock generators are configured to generate the first and second clock signals with equal delays.

6. The integrated circuit of claim 1, further comprising:

a first control signal generator configured to receive the first clock signal and generate a word line control clock (RCLK) signal and an address latch enable (ALE) signal used for read and write operations.

7. The integrated circuit of claim 6, wherein the first control signal generator is configured to generate the ALE signal based on the first clock signal and a reset signal for the first clock generator.

8. The integrated circuit of claim 6, wherein the first control signal generator is configured to further generate a sense amplifier enable (SEN) signal used for read operations.

9. The integrated circuit of claim 6, further comprising:

a second control signal generator configured to receive the second clock signal and generate a data input driver clock (WCLK) signal and a data latch enable (DLE) signal used for write operations.

10. The integrated circuit of claim 9, wherein the second control signal generator is configured to generate the DLE signal based on the second clock signal and a reset signal for the second clock generator.

11. The integrated circuit of claim 9, wherein the first and second control signal generators are configured to generate the RCLK signal and the WCLK signal with equal delays.

12. The integrated circuit of claim 9, wherein the first and second control signal generators are configured to generate the ALE signal and the DLE signal with equal delays.

13. The integrated circuit of claim 1, further comprising:

a reset circuit configured to generate at least one reset signal for the first and second clock generators.

14. The integrated circuit of claim 13, further comprising:

a memory array comprising memory cells and dummy cells, and wherein the reset circuit generates the at least one reset signal with timing determined based on loading on a bit line for a column of dummy cells in the memory array.

15. The integrated circuit of claim 14, wherein the reset circuit generates the at least one reset signal with timing determined further based on loading on a word line for a row of dummy cells in the memory array.

16. The integrated circuit of claim 13, wherein the reset circuit generates the at least one reset signal with a first delay for read operations and with a second delay for write operations.

17. The integrated circuit of claim 13, wherein the reset circuit comprises

a driver having configurable drive strength to obtain different delays for the at least one reset signal for read and write operations.

18. The integrated circuit of claim 13, wherein the reset circuit comprises

a delay unit configured to provide programmable delay for the at least one reset signal.

19. The integrated circuit of claim 13, further comprising:

a power-on reset circuit configured to receive the first and second clock signals and generate a third clock signal for the reset circuit, the power-on reset circuit resetting the first and second clock signals to a known logic level at power on.

20. A method comprising:

generating a first clock signal used for read and write operations; and

generating a second clock signal used for write operations, the first and second clock signals having equal delays.

21. The method of claim 20, further comprising:

generating at least one reset signal having timing determined based on a plurality of dummy cells.

22. The method of claim 20, further comprising:

generating a word line control clock (RCLK) signal and an address latch enable (ALE) signal for read and write operations based on the first clock signal.

23. The method of claim 22, further comprising:

generating a data input driver clock (WCLK) signal and a data latch enable (DLE) signal for write operations based on the second clock signal, the RCLK and WCLK signals having equal delays.

24. An apparatus comprising:

means for generating a first clock signal used for read and write operations; and

means for generating a second clock signal used for write operations, the first and second clock signals having equal delays.

25. The apparatus of claim 24, further comprising:

means for generating at least one reset signal having timing determined based on a plurality of dummy cells.

26. The apparatus of claim 24, further comprising:

means for generating a word line control clock (RCLK) signal and an address latch enable (ALE) signal for read and write operations based on the first clock signal.

27. The apparatus of claim 26, further comprising:

means for generating a data input driver clock (WCLK) signal and a data latch enable (DLE) signal for write operations based on the second clock signal, the RCLK and WCLK signals having equal delays.

28. An integrated circuit comprising:

a clock generator configured to generate a first clock signal used for read and write operations;

a control signal generator configured to receive the first clock signal and generate a second clock signal used for write operations, the second clock signal being enabled only for write operations; and

a reset circuit configured to generate a reset signal for the clock generator, the reset signal having timing determined based on loading due to a plurality of dummy cells.

29. The integrated circuit of claim 28, wherein the reset circuit is configured to generate the reset signal with different delays for read and write operations.

30. An integrated circuit comprising:

a clock generator configured to receive an external clock signal and generate an internal clock signal;

a reset circuit configured to generate a reset signal for the clock generator; and

a control signal generator configured to generate a latch enable signal having pulse width determined based on the internal clock signal and the reset signal.

31. The integrated circuit of claim 30, wherein the latch enable signal is an address latch enable (ALE) signal used to latch an address for read or write operation.

32. The integrated circuit of claim 30, wherein the latch enable signal is a data latch enable (DLE) signal used to latch input data for write operation.

33. The integrated circuit of claim 30, further comprising:

a memory array comprising memory cells and dummy cells, and wherein the reset circuit generates the reset signal with timing determined based on loading due to the dummy cells in the memory array.

34. The integrated circuit of claim 30, wherein the control signal generator generates the latch enable without using a one-shot circuit.