APPARATUS FOR QUEUE MANAGEMENT OF A GLOBAL LINK CONTROL BYTE IN AN INPUT/OUTPUT SUBSYSTEM

• US 20080298381A1
• Filed: 08/11/2008
• Published: 12/04/2008
• Est. Priority Date: 12/11/2003
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jestes, Roger C. JR.
• Application Number:
  US12/189,646
• Publication Number:
  US 20080298381A1
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet

Abstract

Apparatus for communicating global link control words (LCW) between chips. A queue stores LCWs and has an input for receiving an LCW from a previous chip, and an output for outputting a stored LCW to a subsequent chip. A management circuit compares an incoming LCW with a previously stored LCW, and a combiner circuit combines the incoming LCW with a previously stored LCW and stores the combined LCW in the queue when the management circuit determines that the incoming LCW can be combined with the previously stored LCW.

Claims

1. An apparatus for communicating global link control words (LCW) between chips, said apparatus comprising:

a queue for storing an LCW, said queue having an input for receiving an LCW from a previous chip, and an output for outputting a stored LCW to a subsequent chip;

a management circuit for comparing an incoming LCW with a previously stored LCW; and

a combiner circuit for combining the incoming LCW with a previously stored LCW and storing the combined LCW in said queue when said management circuit determines that the incoming LCW can be combined with the previously stored LCW such that more than one LCW are combined and the combined LCW is stored in an element of said queue.

2. The apparatus according to claim 1 wherein said queue has multiple elements, and said combiner circuit stores said incoming LCW in a separate queue element when said management circuit determines the incoming LCW cannot be combined with the previously stored LCW.

3. The apparatus according to claim 1 wherein each LCW comprises bits and said combiner circuit comprises an OR circuit for combining the bits of said incoming LCW with the bits of said previously stored LCW.

4. The apparatus according to claim 3 wherein said management circuit places a control bit in a first state indicating that an incoming LCW cannot be combined with another LCW previously stored in said queue for controlling storing said incoming LCW in a separate element in said queue, and said management circuit places said control bit in a second state indicating said incoming LCW can be combined with another LCW previously stored in said queue.

5. The apparatus according to claim 3 wherein at least two selected bits of said LCWs have an Exclusive OR relationship wherein either of the bits may be on, but not both, and said management circuit controls the combiner circuit such that two LCWs will not be combined if the Exclusive OR relationship is violated.