INTEGRATED CIRCUIT DIE WITH LOGICALLY EQUIVALENT BONDING PADS

• US 20080299704A1
• Filed: 06/12/2008
• Published: 12/04/2008
• Est. Priority Date: 11/10/2004
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: RONEN, Amir
• Granted Patent: US 7,863,093 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multchip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.

Claims

1. A method of producing system-in-package devices, comprising the steps of:

(a) providing two substantially identical first integrated circuit dies, each said first integrated circuit die having a plurality of bonding pads, wherein two of said bonding pads share a common logical function;

(b) providing a second integrated circuit die that is functionally different from said first integrated circuit dies, said second integrated circuit die having a plurality of bonding pads;

(c) providing a third integrated circuit die that is functionally identical to said second integrated circuit die, said third integrated circuit die having a plurality of bonding pads, said bonding pads of said third integrated circuit die having a different geometric arrangement than said bonding pads of said second integrated circuit die;

(d) producing a first system-in-package device by steps including directly electrically connecting a first of said two bonding pads, of one of said first integrated circuit dies, that share said common logical function, to one of said bonding pads of said second integrated circuit die; and

(e) producing a second system-in-package device by steps including directly electrically connecting a second of said two bonding pads, of another of said first integrated circuit dies, that share said common logical function, to one of said bonding pads of said third integrated circuit die, wherein said one bonding pad of said third integrated circuit die is functionally identical to but geometrically different than said one bonding pad of said second integrated circuit die.

2. The method of claim 1, wherein said first integrated circuit dies are memory dies and said second and third integrated circuit dies are processor dies.

3. The method of claim 1, wherein said first integrated circuit dies are processor dies and said second and third integrated circuit dies are memory dies.

4. A method of producing multichip package devices, comprising the steps of:

(a) providing a plurality of substantially identical first integrated circuit dies, each said first integrated circuit die having a plurality of bonding pads, wherein two of said bonding pads share a common logical function;

(b) providing a plurality of second integrated circuit dies, each said second integrated circuit die having a plurality of bonding pads;

(c) producing a first multichip package device by steps including;

(i) mounting one of said first integrated circuit dies in a stacked relationship with one of said second integrated circuit dies, and

(ii) directly electrically connecting a first of said two bonding pads of said one first integrated circuit die that share said common logical function to a first of said bonding pads of said one second integrated circuit die; and

(d) producing a second multichip package device by steps including;

(i) mounting another of said first integrated dies in a stacked relationship with another of said second integrated circuit dies, and

(ii) directly electrically connecting a second of said two bonding pads of said other first integrated circuit die that share said common logical function to a second of said bonding pads of said other second integrated circuit die.