Carbon Nanotube Transistor Fabrication

• US 20080299710A1
• Filed: 10/11/2007
• Published: 12/04/2008
• Est. Priority Date: 09/16/2004
• Status: Active Grant

• Current Assignee: Etamota Corporation
• Original Assignee: Atomate Corporation
• Inventors: Tombler, Thomas W. JR., Lim, Brian Y.
• Granted Patent: US 7,736,943 B2
• Time in Patent Office: Days
• US Class Current: 438/142
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10K 10/491 Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer
• CPC Class Codes: Y10S 977/843 Gas phase catalytic growth, i.e. chemical vapor deposition
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region
• CPC Class Codes: Y10S 977/962 for carrying or transporting

Abstract

During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.

Claims

1. A method of making a transistor device comprising:

providing a template comprising a plurality of pores, each pore having a pore diameter;

exposing the template having pores to a hydrocarbon gas at a temperature to grow carbon nanotubes in the pores, each carbon nanotube having an outer diameter less than the pore diameter in the template in which the carbon nanotube is produced;

forming a first electrode region to electrically couple to first ends of the carbon nanotubes;

forming a second electrode region to electrically couple to second ends of the carbon nanotubes;

forming a first trench in the template; and

forming a first gate region in the first trench.

2. The method of claim 1 comprising:

forming a second trench in the template, wherein between the first and second trenches are at least two carbon nanotubes in the template; and

forming a second gate region in the second trench.

3. The method of claim 2 wherein the first and second gate regions are electrically coupled together to form a gate electrode of the transistor device.

4. The method of claim 1 wherein the first gate region extends into the template.

5. The method of claim 1 wherein the first trench has a depth from about 50 nanometers to about 1000 nanometers.

6. The method of claim 1 wherein the first gate region is not electrically shorted to the carbon nanotubes below the first gate region.

7. The method of claim 1 wherein the first gate region comprises polysilicon.

8. The method of claim 1 wherein the first gate region comprises a conductive material.

9. The method of claim 1 wherein the template comprises at least one of alumina, silicon, silicon germanium, gallium nitride, germanium, gallium arsenide, silicon oxide, plastic, polymer, glass, or quartz.

10. The method of claim 1 wherein the template is provided on a substrate.

11. The method of claim 10 wherein the substrate is at least one of silicon, silicon germanium, gallium nitride, germanium, gallium arsenide, silicon oxide, plastic, polymer, glass, quartz, metal, copper, molybdenum, aluminum, or tungsten.

12. The method of claim 1 wherein the template is provided on a substrate and the substrate is a different material than the template.

13. The method of claim 1 wherein the template is an insulator material and is provided on a substrate that is a conductor material.

14. The method of claim 1 further comprising:

before exposing the template containing pores to a hydrocarbon gas, depositing a catalyst into the pores.

15. The method of claim 14 wherein the catalyst is at least one of cobalt or an alloy of cobalt.

16. The method of claim 14 wherein the catalyst is at least one of iron or an alloy of iron.

17. The method of claim 14 wherein the catalyst is at least one of nickel or an alloy of nickel.

18. The method of claim 1 wherein the exposing the template containing pores to a hydrocarbon gas occurs at a temperature in a range from about 750 degrees Celsius to about 850 degrees Celsius.

19. The method of claim 1 wherein the exposing the template containing pores to a hydrocarbon gas occurs at a temperature in a range from about 600 degrees Celsius to about 1000 degrees Celsius.

20. The method of claim 1 wherein the carbon nanotubes grown comprise semiconducting and metallic carbon nanotubes, and the method further comprises:

exposing the template with carbon nanotubes to a reagent, whereby the reagent renders greater numbers of the metallic carbon nanotubes ineffective for transistor operation than semiconducting carbon nanotubes.

21. The method of claim 20 wherein the reagent is an acid.

22. The method of claim 20 wherein the reagent is nitric acid.

23. The method of claim 1 wherein the carbon nanotubes grown comprise semiconducting and metallic carbon nanotubes, and the method further comprises:

applying a voltage to the first gate region that results in a current flow through the carbon nanotubes, whereby the metallic carbon nanotubes are burned off in greater numbers than the semiconducting carbon nanotubes.

24. The method of claim 23 wherein the current flow through a metallic carbon nanotube is at least 15 microamps.

25. The method of claim 23 wherein the current flow through a metallic carbon nanotube is from about 15 microamps to about 25 microamps.