SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS

• US 20080299726A1
• Filed: 05/29/2008
• Published: 12/04/2008
• Est. Priority Date: 05/29/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: KAWASHIMA, Yoshiya, MIURA, Yoshinao, NINOMIYA, Hitoshi
• Granted Patent: US 7,829,417 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.

Claims

1. A method of manufacturing a semiconductor apparatus with a superjunction structure including a column region, comprising:

forming a gate electrode in a mesh pattern in a semiconductor layer;

forming a photo resist pattern for forming an ion implantation region in the semiconductor layer, the photo resist pattern being formed by using a photomask, the photomask having a compensation pattern in such a way that the compensation pattern is surrounded by the gate electrode in a plane view and a distance from one linear edge of the gate electrode to the compensation pattern is gradually-changed depending on a location on the one linear edge of the gate electrode;

forming the ion implantation region by using the photo resist pattern; and

performing heat treatment on the semiconductor layer.

2. The method of manufacturing a semiconductor apparatus according to claim 1, wherein the compensation pattern is designed so as to compensate a deformation of the photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by the heat treatment.

3. The method of manufacturing a semiconductor apparatus according to claim 1, wherein

the gate electrode in a mesh pattern is formed in a polygonal shape, and

the outer edge of the ion implantation region is closest to the gate electrode at a portion corresponding to a corner of the gate electrode in the polygonal shape.

4. The method of manufacturing a semiconductor apparatus according to claim 1, wherein

the gate electrode in a mesh pattern is formed in a polygonal shape,

the outer edge of the ion implantation region has a first distance to the gate electrode at a portion corresponding to a corner of the gate electrode in the polygonal shape, and

the outer edge of the ion implantation region has a second distance being longer than the first distance at a middle of a side of the gate electrode in the polygonal shape.

5. The method of manufacturing a semiconductor apparatus according to claim 3, wherein

the gate electrode in a mesh pattern is formed in a polygonal shape,

the outer edge of the ion implantation region has a first distance to the gate electrode at a portion corresponding to a corner of the gate electrode in the polygonal shape, and

the outer edge of the ion implantation region has a second distance being longer than the first distance at a middle of a side of the gate electrode in the polygonal shape.

6. The method of manufacturing a semiconductor apparatus according to claim 1, wherein

the outer edge of the ion implantation region has a first distance to the gate electrode at an edge corresponding to a plane equivalent to a (100) plane in the plane direction, and

the outer edge of the ion implantation region has a second distance being longer than the first distance at a middle of a side of the gate electrode in the polygonal shape.

7. The method of manufacturing a semiconductor apparatus according to claim 3, wherein

the outer edge of the ion implantation region has a first distance to the gate electrode at an edge corresponding to a plane equivalent to a (100) plane in the plane direction, and

the outer edge of the ion implantation region has a second distance being longer than the first distance at a middle of a side of the gate electrode in the polygonal shape.

8. The method of manufacturing a semiconductor apparatus according to claim 4, wherein

the outer edge of the ion implantation region has a first distance to the gate electrode at an edge corresponding to a plane equivalent to a (100) plane in the plane direction, and

the outer edge of the ion implantation region has a second distance being longer than the first distance at a middle of a side of the gate electrode in the polygonal shape.