SYSTEM INCLUDING A FINE-GRAINED MEMORY AND A LESS-FINE-GRAINED MEMORY

• US 20080301256A1
• Filed: 05/30/2008
• Published: 12/04/2008
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Schooner Information Technology, Inc. (Western Digital Corporation)
• Inventors: Cohen, Earl T., McWilliams, Thomas M., Bodwin, James M., Bruening, Ulrich
• Granted Patent: US 7,975,109 B2
• Time in Patent Office: Days
• US Class Current: 709/214
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses n node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

Claims

1. A system comprising:

a plurality of nodes, each of the nodes comprising

a respective processor,

a respective interconnect switch,

a respective fine-grained memory comprising a plurality of independently-writable words, and

a respective less-fine-grained memory comprising a plurality of independently-writable pages, where units of the respective less-fine-grained memory smaller than one of the pages are not independently writable, where each of the pages is at least twice a size of one of the words of the fine-grained memory, and where the respective less-fine-grained memory is a solid-state, non-volatile memory;

an interconnection network coupling the nodes via the respective interconnect switches;

wherein the less-fine-grained memories as an aggregate are configured to store a plurality of elements, each of the elements having a respective element identifier;

wherein the respective fine-grained-memory of each of at least a first subset of the nodes is enabled to store a respective global map, the respective global map configured to specify for each of the elements, based at least in part on a portion of the respective element identifier, a respective home one of the nodes of the element;

wherein, at each of the nodes,

the respective less-fine-grained memory is enabled to store a respective subset of the elements, and

the respective fine-grained-memory is enabled to store a respective local map, the respective local map having a plurality of entries, each one of the respective subset of the elements associated with a corresponding and distinct one of the entries, each of the entries comprising fields which when populated store a respective physical location of the element associated with the entry, the respective physical location comprising an address of a respective one of the pages of the respective less-fine-grained memory and a respective offset within the respective page;

wherein, at a particular one of the first subset of the nodes, the respective processor is configured to

determine, via the respective global map, the respective home node of a particular one of the elements, and

forward an access of the particular element to the respective processor of the respective home node of the particular element;

wherein, at the respective home node of the particular element, the respective processor is configured to

access, via the respective local map, the respective physical location of the particular element in the respective less-fine-grained memory, and

return a response to the access of the particular element to the respective processor of the particular node; and

wherein the particular element and at least one other of the respective subset of the elements of the respective home node of the particular element are enabled to be stored at a same time in the respective page of the respective physical location of the particular element.

2. The system of claim 1, wherein the elements are not all of a same size.

3. The system of claim 2, wherein the particular element and the at least one other of the elements are different in size.

4. The system of claim 2, wherein at least some of the elements are less than 128 bytes in size.

5. The system of claim 2, wherein at least some of the elements are enabled to have a size in a range from a minimum size to a maximum size.

6. The system of claim 1,

wherein the access is a write access;

wherein the particular element is associated with a particular one of the entries of the respective local map of the respective home node of the particular element, the particular entry enabled, prior to the write access, to store a first one of the physical locations;

wherein the respective processor of the respective home node of the particular element is further configured, in conjunction with the write access, to update the particular entry to store a second one of the physical locations; and

wherein the respective page of the first physical location is different from the respective page of the second physical location.

7. The system of claim 6, wherein the respective offset of the first physical location is different from the respective offset of the second physical location.

8. The system of claim 7, wherein the respective offset of the first physical location is an index within the respective page of the first physical location, the index having a granularity of no more than 64 bytes.

9. The system of claim 6,

wherein the particular node is a first one of the nodes;

wherein, at a second one of the nodes, the respective processor is configured, subsequent to completion of the write access, to access the at least one other of the elements by, at least in part, forwarding the access of the at least one other of the elements to the respective processor of the respective home node of the particular element; and

wherein, at the respective home node of the particular element, the respective processor is configured to

access, via the respective local map, the respective physical location of the at least one other of the elements in the respective less-fine-grained memory, and

where the respective page of the respective physical location of the at least one other of the elements is the respective page of the first physical location.

10. The system of claim 9, wherein the second node is different from the first node.

11. The system of claim 9, wherein the particular element and the at least one other of the elements are different in size.

12. The system of claim 9, wherein the respective processor of the respective home node of the particular element is further configured, in conjunction with the write access, to

store data of the write access in a particular one of a plurality of pages of a write buffer in the respective fine-grained memory of the respective home node of the particular element, and

copy, subsequent to the storing of the data of the write access, the particular page of the write buffer to the respective page of the second physical location in the respective less-fine-grained memory of the respective home node of the particular element.

13. The system of claim 12, wherein the respective home node of the particular element further comprises a back-up power source coupled to the write buffer.

14. The system of claim 13, wherein at least a portion of the respective fine-grained memory of the respective home node of the particular element is not coupled to the back-up power source, the at least a portion of the respective fine-grained memory of the respective home node of the particular element comprising the respective local map of the respective home node of the particular element.

15. The system of claim 13,

wherein the respective home node of the particular element further comprises a primary power source coupled to the respective fine-grained memory of the respective home node of the particular element;

and

wherein the respective processor of the respective home node of the particular element is further configured, in event of a power disruption of the primary power source, to copy the particular page of the write buffer to a determined one of the pages of the respective less-fine-grained memory of the respective home node of the particular element.

16. The system of claim 15, wherein the determined page of the respective less-fine-grained memory of the respective home node of the particular element is the respective page of the second physical location.

17. The system of claim 6, wherein the respective processor of the respective home node of the particular element comprises a memory controller, the memory controller coupled to the respective less-fine-grained memory of the respective home node of the particular element.

18. The system of claim 17, wherein, in conjunction with the write access, the memory controller is configured to compress the particular element.

19. The system of claim 18, wherein, subsequent to the write access, a size of a read access to the respective physical location of the particular element in the respective less-fine-grained memory of the respective home node of the particular element varies according to a compression ratio achieved by the memory controller.

20. The system of claim 1, wherein the particular node is the respective home node of the particular element.

21. The system of claim 1, wherein the respective offset of the respective physical location of the particular element is an index of an independently read-accessible storage location.

22. The system of claim 1, wherein each of the elements is enabled to be stored within one of the respective less-fine-grained memories.

23. The system of claim 1, wherein each of at least some of the elements is enabled to be stored within a first one of the respective less-fine-grained memories, and is further enabled to have a respective replica stored within a second one of the respective less-fine-grained memories, the second less-fine-grained memory different from the first less-fine-grained memory.

24. The system of claim 1, wherein each of the elements smaller in size than one half of a size of one of tire pages of a particular one of the less-fine-grained memories is enabled to be stored along with a respective error detecting code in the particular less-fine-grained memory.

25. The system of claim 24, wherein the respective error detecting code is a Cyclic Redundancy Check (CRC).

26. The system of claim 24, wherein the respective error detecting code is an error correcting code.

27. The system of claim 24, wherein a type of the respective error detecting code is according to a size of the element.

28. The system of claim 24, wherein each of the pages of the particular less-fine-grained memory enabled to store more than one of the elements is further enabled to store an error correcting code protecting the more than one of the elements, the error correcting code different from the respective error detecting codes of the more than one of the elements.

29. The system of claim 28, wherein the error correcting code comprises an independent error correcting code for each of a plurality of sub-pages of the page.

30. The system of claim 28, wherein the error correcting code comprises the respective error detecting codes of at least one of the more than one of the elements.

31. The system of claim 1, wherein the first subset of the nodes is two or more of the nodes.

32. The system of claim 1, wherein the first subset of the nodes is all of the nodes.

33. The system of claim 1, wherein the respective interconnect switch comprises a Network Interface Controller (NIC).

34. The system of claim 33, wherein the interconnection network comprises a network switch.

35. The system of claim 1, wherein the respective less-fine-grained memory of the particular node comprises at least one flash memory chip.

36. The system of claim 1, wherein each one of the respective subset of the elements is associated with the corresponding entry of the respective local map via at least a portion of the respective element identifier.

37. The system of claim 1, wherein the respective element identifier of the particular element comprises an address of the particular element.

38. The system of claim 37, wherein the address is an address in a node address space.

39. The system of claim 1, wherein the respective element identifier of the particular element comprises a text string.

40. The system of claim 39, wherein, for each of at least some of the elements including the particular element, the less-fine-grained memories as an aggregate are further configured to store the respective element identifier along with the element.

41. The system of claim 40, wherein the respective element identifiers of the at least some of the elements are not all of a same size.

42. The system of claim 1, wherein the respective offset is an index within the respective page, the index having a granularity of no more than 32 bytes.

43. A memory system comprising:

a non-volatile memory comprising a plurality of pages, where units of the memory smaller than one of the pages of the memory are not independently writable, and where each of the pages of the memory comprises a respective user-accessible portion;

a map configured to associate respective element identifiers of each of a plurality of elements with a respective physical location of the element in the memory, where the respective physical location comprises an address of a respective one of the pages of the memory and a respective offset within the respective page of the memory;

a coalescing buffer comprising a plurality of pages, a size of each of the pages of the coalescing buffer being sufficient to contain the respective user-accessible portion of one of the pages of the memory;

wherein the memory system is configured to write a first one of the elements to the memory by

storing the first element in a first portion of a particular one of the pages of the coalescing buffer,

copying the particular page of the coalescing buffer to a particular one of the pages of the memory, and

updating the map so that the address of the respective page of the respective physical location of the first element is an address of the particular page of the memory, and so that the respective offset of the respective physical location of the first element is according to the first portion of the particular page of the coalescing buffer; and

wherein the memory system is further configured, subsequent to the storing of the first element in the particular page of the coalescing buffer and prior to the copying of the particular page of the coalescing buffer to the particular page of the memory, to store a second one of the elements in a second portion of the particular page of the coalescing buffer, the second element different from the first element, the second portion separate from the first portion.

44. The system of claim 43, wherein the elements are not all of a same size.

45. The system of claim 44, wherein the first element and the second element are different in size.

46. The system of claim 43, wherein the memory system is further configured, in conjunction with the storing of the first element in the particular page of the coalescing buffer, to store a respective error detecting code covering the first element in the particular page of the coalescing buffer.

47. The system of claim 46, wherein the respective error detecting code is a Cyclic Redundancy Check (CRC).

48. The system of claim 46,

wherein the memory system is further configured to write the first element to the memory by copying the particular page of the coalescing buffer to the respective user-accessible portion of the particular page of the memory;

and

wherein the respective user-accessible portion of the particular page of the memory is enabled to store the respective error detecting code covering the first element along with the first element.

49. The system of claim 48,

wherein each of the pages of the memory is associated with a respective overhead portion distinct from the respective user-accessible portion;

and

wherein the respective overhead portion of the particular page of the memory is enabled to store an error correcting code protecting at least some of the respective user-accessible portion of the particular page.

50. The system of claim 49, wherein each of the pages of the memory further comprises the respective overhead portion.

51. The system of claim 49, wherein a block of the memory containing the particular page of the memory comprises the respective overhead portion of the particular page of the memory.

52. The system of claim 51, wherein the respective user-accessible portion of the particular page of the memory is all of the particular page of the memory.

53. The system of claim 49, wherein, subsequent to the copying of the particular page of the coalescing buffer to the respective user-accessible portion of the particular page of the memory, the error correcting code is enabled to protect the first element and the second element.

54. The system of claim 49, wherein the memory system is further configured to read the first element by

using the map to associate the respective element identifier of the first element with the respective physical location of the first element, the respective page of the respective physical location of the first element being the particular page of the memory, and

retrieving a portion less than all of the respective user-accessible portion of the particular page of the memory according to the respective offset of the respective physical location of the first element.

55. The system of claim 54,

wherein the portion less than all is a first portion less than all;

and

wherein a second portion less than all of the respective user-accessible portion of the particular page of the memory is enabled to store at least a part of the second element, the second portion less than all distinct from the first portion less than all.

56. The system of claim 55, wherein the first element and the second element are different in size.

57. The system of claim 54,

wherein the portion less than all of the particular page of the memory is enabled to store the respective error detecting code covering the first element;

and

wherein the memory system is further configured to read the first element by detecting a presence of an error in the first element as stored in the portion less than all using the respective error detecting code as stored in the portion less than all.

58. The system of claim 57, wherein the memory system is further configured, in response to the detecting of the presence of the error in the first element as stored in the portion less than all, to

retrieve a second portion of the memory, the second portion comprising the error correcting code, and

use the error correcting code to correct the error in the first element as stored in the portion less than all.

59. The system of claim 46, wherein the memory system is further configured to read the first element from the first portion of the particular page of the coalescing buffer.

60. The system of claim 59, wherein the memory system is enabled to use the coalescing buffer as a cache of the memory.

61. The system of claim 43, wherein the memory system is further configured to determine the particular page of the coalescing buffer.

62. The system of claim 61, wherein the memory system is further configured to determine the particular page of the coalescing buffer according to a respective expected write frequency associated with each of the pages of the coalescing buffer.

63. The system of claim 61, wherein the memory system is further configured to determine the particular page of the coalescing buffer according to a respective expected write frequency associated with the first element.

64. The system of claim 61,

wherein the memory comprises a plurality of shards, each of the shards comprising a respective subset of the pages of the memory;

and

wherein the memory system is further configured to determine the particular page of the coalescing buffer according to the shard containing the particular page of the memory.

65. The system of claim 43,

wherein the particular page of the memory is a first page of the memory;

wherein the memory system is further configured to coalesce a second one of the pages of the memory, the second page of the memory different from the first page of the memory, by

reading, prior to the storing of the first element in the first page of the coalescing buffer, the first element from the second page of the memory, and

erasing, subsequent to the reading of the first element, a block of the memory containing the second page of the memory.

66. The system of claim 65, wherein, prior to the reading of the first element from the second page of the memory, the map is configured so that the address of the respective page of the respective physical location of the first element is an address of the second page of the memory, and so that the respective offset of the respective physical location of the first element is an offset within the second page of the memory.

67. The system of claim 66, wherein the offset within the second page is different from the respective offset according to the first portion of the particular page of the coalescing buffer.

68. The system of claim 43, wherein each of the elements smaller in size than one half of a size of one of the pages of the memory is enabled to be stored along with a respective error detecting code in the respective user-accessible portion of one of the pages of the memory.

69. The system of claim 68, wherein each of the elements larger in size than a specified minimum size and smaller in size than one half of a size of one of the pages of the memory is enabled to be stored along with a respective error detecting code in the respective user-accessible portions of a contiguous, with respect to addresses of the memory, pair of the pages of the memory.

70. The system of claim 68, wherein the memory system is further configured to compute the respective error detecting code.

71. The system of claim 68,

wherein each of the pages of the memory is associated with a respective overhead portion, the respective overhead portion distinct from the respective user-accessible portion;

and

wherein the respective overhead portion of the particular page of the memory is enabled to store an error correcting code protecting the respective user-accessible portion of the particular page.

72. The system of claim 71, wherein each of the pages of the memory further comprises the respective overhead portion.

73. The system of claim 71,

wherein the memory comprises a plurality of blocks, each of the blocks comprising a respective one or more of the pages of the memory;

and

wherein one of the blocks of the memory comprising the particular page of the memory comprises the respective overhead portion of the particular page of the memory.

74. The system of claim 73, wherein the respective user-accessible portion of the particular page of the memory is all of the particular page of the memory.

75. The system of claim 73, wherein a minimum erasable unit of the memory is one of the blocks of the memory.

76. The system of claim 43, wherein the memory is organized as a plurality of erasable blocks, each of the blocks comprising a respective one or more of the pages of the memory.

77. The system of claim 43,

wherein the map comprises a plurality of entries, each of elements corresponding to a distinct one of the entries, the respective element identifier associated with the corresponding entry;

and

wherein each of the entries is enabled to store the respective physical location of the one of the elements corresponding to the entry.

78. The system of claim 43, wherein the respective offset is an index within the respective page of the memory, the index having a granularity of no more than 64 bytes.

79. The system of claim 78, wherein the respective offset is an index within the respective page of the memory, the index having a granularity of no more than eight bytes.

80. The system of claim 43, further comprising a Direct Memory Access (DMA) controller, the DMA controller enabled to perform the copying of the particular page of the coalescing buffer to the particular page of the memory.

81. The system of claim 43,

wherein the memory is part of a particular one or more semiconductor devices;

and

wherein the coalescing buffer is part of one or more semiconductor devices separate from the particular semiconductor devices.

82. A method comprising:

mapping, via a map comprising a plurality of entries, each of a plurality of elements associated via a respective element identifier with a corresponding and distinct one of the entries, the respective element identifier of a particular one of the elements to determine a respective physical location of the particular element in a non-volatile memory, where the non-volatile memory comprises a plurality of pages, where units of the non-volatile memory smaller than one of the pages are not independently writable, and where the respective physical location of the particular element comprises an address of a particular one of the pages and an offset within the particular page;

reading the particular element by retrieving a first portion less than all of the particular page according to the offset, and where at least one of the elements other than the particular element is stored in a second portion of the particular page, the second portion exclusive of the first portion; and

determining if the first portion has an error using a respective portion-specific error-detecting code of the first portion, the respective portion-specific error-detecting code of the first portion stored in the first portion.

83. The method of claim 82, wherein the non-volatile memory is a solid-state memory.

84. The method of claim 82, wherein a size of the particular element is different than a size of one of the at least one of the elements.

85. The method of claim 82, wherein the first portion is a contiguous portion.

86. The method of claim 82, further comprising providing as at least part of an access to the particular element in the non-volatile memory, the respective element identifier of the particular element.

87. The method of claim 86, wherein the providing is by software executing on a processor.

88. The method of claim 87, wherein the software is an application.

89. The method of claim 86,

wherein the retrieving the first portion of the particular page is in response to the providing;

and

further comprising retrieving at least a portion of an other one of the pages of the non-volatile memory, the other page different from the particular page, subsequent to the retrieving the first portion of the particular page and prior to retrieving any of the second portion of the particular page.

90. The method of claim 82,

wherein the particular element is a first element, the offset is a first offset, and the at least one of the elements is a second element;

and

further comprising;

retrieving the second portion of the particular page according to a second offset within the particular page, the second offset different from the first offset, and

determining if the second portion has an error using a respective portion-specific error-detecting code of the second portion, the respective portion-specific error-detecting code of the second portion stored in the second portion.

91. The method of claim 90, wherein a size of the first element is different than a size of the second element.

92. The method of claim 90, further comprising mapping the respective element identifier of the second element to determine a respective physical location of the second element in the non-volatile memory, where the respective physical location of the second element comprises the address of the particular page and the second offset.

93. The method of claim 82, wherein the respective portion-specific error-detecting code of the first portion is a Cyclic Redundancy Check (CRC).

94. The method of claim 82, further comprising, in response to determining that the first portion has the error, using an error correcting code stored in the particular page to correct the error.

95. The method of claim 94, further comprising storing the error correcting code in a portion of the particular page exclusive of the first portion and exclusive of the second portion.

96. The method of claim 94, wherein the error correcting code protects the first portion of the particular page and the second portion of the particular page.

97. The method of claim 94, further comprising using the respective portion-specific error-detecting code of the first portion solely to determine if the first portion has the error.

98. The method of claim 94, wherein the error correcting code comprises the respective portion-specific error-detecting code of the first portion and at least one other error-detecting code stored in the particular page.

99. The method of claim 82, wherein the corresponding entry of the particular element stores the respective physical location of the particular element.

100. The method of claim 99,

further comprising, prior to the reading, writing the particular element;

and

wherein the writing comprises storing the address of the particular page and the offset within the particular page in the corresponding entry of the particular element.

101. The method of claim 99,

further comprising, subsequent to the reading, writing the particular element;

and

wherein the writing comprises updating the corresponding entry of the particular element so that the respective physical location of the particular element is an updated physical location.

102. The method of claim 101,

wherein the particular page is a first page, and the offset within the particular page is a first offset;

and

wherein the updated physical location comprises an address of a second one of the pages and a second offset within the second page, the second page different from the first page, and the second offset different from the first offset.

103. The method of claim 102, wherein the writing further comprises:

writing solely a first part less than all of the particular element to the second page; and

writing a remaining part of the particular element to a third one of the pages, the third page different from the first page, and the third page different from the second page.

104. The method of claim 103, wherein the third page is in a same one of a plurality of blocks of the non-volatile memory as the second page, and the third page is adjacent, with respect to addresses of the non-volatile memory, to the second page.

105. The method of claim 103, wherein the third page is in a different one of a plurality of blocks of the non-volatile memory than the second page, and the updated physical location further comprises an address of the third page.

106. The method of claim 82,

further comprising, prior to the reading, writing the particular element;

and

wherein the writing comprises computing the respective portion-specific error-detecting code of the first portion.

107. The method of claim 106, wherein the writing further comprises computing a respective page-specific error-correcting code of the particular page.

108. The method of claim 107, wherein the writing further comprises storing the page-specific error-correcting code in a portion of the particular page exclusive of the first portion and exclusive of the second portion.

109. The method of claim 108, wherein the writing further comprises writing the particular element and the respective portion-specific error-detecting code of the first portion to a region of a write buffer in a volatile memory, and copying the region of the write buffer to the particular page.

110. The method of claim 109, further comprising, in event of a power disruption of a primary power source coupled to the volatile memory, powering the volatile memory with a back-up power source.

111. The method of claim 82, wherein the offset specifies an index within the particular page, the index having a granularity of no more than 64 bytes.

112. The method of claim 111, wherein the offset specifies an index within the particular page, the index having a granularity of no more than eight bytes.

113. The method of claim 82, wherein the elements are not all of a same size.

114. The method of claim 82, wherein the element identifiers specify sections of an address space.

115. The method of claim 114, wherein the element identifiers are addresses of the sections of the address space.

116. The method of claim 82, wherein the element identifiers are keys.

117. The method of claim 116, wherein the keys are text strings.

118. The method of claim 116, wherein the keys are not all of a same size.

119. A method comprising:

coalescing a first one of a plurality of logical partitions stored in a first one of a plurality of pages of a non-volatile, less-fine-grained memory and a second one of the logical partitions stored in a second one of the pages of the less-fine-grained memory into separate regions in a particular page of a write buffer in a volatile, fine-grained memory, where each of the pages of the less-fine-grained memory is enabled to store a respective two or more of the logical partitions, and where a minimum writable unit of the less-fine-grained memory is one of the pages of the less-fine-grained memory;

writing, subsequent to the coalescing, the particular page of the write buffer to a third one of the pages of the less-fine-grained memory, where the first page, the second page, and the third page are all different ones of the pages of the less-fine-grained memory; and

maintaining a map comprising a plurality of entries, each of the entries associating a respective one of a plurality of elements with a respective one of the logical partitions of a respective one of the pages of the less-fine-grained memory, and where prior to the writing, a first one of the elements is associated with the first logical partition via a first one of the entries of the map, and a second one of the elements is associated with the second logical partition via a second one of the entries of the map.

120. The method of claim 119, wherein the less-fine-grained memory is a solid-state memory.

121. The method of claim 119, wherein a size of the first logical partition is different from a size of the second logical partition.

122. The method of claim 119, wherein the maintaining comprises updating the first entry to associate the first element with a third one of the logical partitions stored in the third page of the less-fine-grained memory.

123. The method of claim 122, wherein the updating the first entry comprises updating an offset stored in the first entry to be an offset of the third logical partition stored in the third page of the less-fine-grained memory.

124. The method of claim 123,

wherein prior to the updating the first entry, the offset stored in the first entry is an offset of the first logical partition stored in the first page of the less-fine-grained memory;

and

wherein the offset of the third logical partition is different from the offset of the first logical partition.

125. The method of claim 123, wherein the offset stored in the first entry has a granularity of no more than 64 bytes.

126. The method of claim 123, wherein the offset stored in the first entry has a granularity of no more than eight bytes.

127. The method of claim 122, further comprising:

reading, prior to the coalescing, the first element from the first page of the less-fine-grained memory; and

reading, subsequent to the writing, the first element from the third page of the less-fine-grained memory.

128. The method of claim 122,

wherein each of the first logical partition, the second logical partition, and the third logical partition stores a respective error detecting code;

and

wherein the writing comprising storing in the third page of the less-fine-grained memory a respective error correcting code protecting contents of the third page of the less-fine-grained memory including the third logical partition, and where the respective error correcting code of the third page of the less-fine-grained memory is different from the respective error detecting code of the third logical partition.

129. The method of claim 119, wherein the particular page of the write buffer is one of a plurality of pages of the write buffer.

130. The method of claim 119, wherein the first logical partition stores data of the first element in a compressed form.

131. The method of claim 130, wherein the first logical partition further stores a header of the compressed data of the first element.

132. The method of claim 131, wherein the header comprises a type of compression used to produce the compressed form.

133. The method of claim 131, wherein the header comprises a size of the compressed data of the first element.

134. The method of claim 119, wherein the coalescing comprises storing at least a portion of the first logical partition into the particular page of the write buffer, and subsequently storing at least a portion of the second logical partition into the particular page of the write buffer.

135. The method of claim 134, wherein the coalescing further comprises:

computing a respective error detecting code for each of the at least a portion of the first logical partition and the at least a portion of the second logical partition; and

storing the respective error detecting codes into the particular page of the write buffer.

136. The method of claim 134,

wherein the first logical partition comprises a respective error detecting code;

and

wherein the at least a portion of the first logical partition is all of the first logical partition.

137. The method of claim 119, wherein, prior to the coalescing, the first page of the less-fine-grained memory stores at least two of the logical partitions.

138. The method of claim 119, further comprising, subsequent to the coalescing, erasing a block of the less-fine-grained memory containing the first page of the less-fine-grained memory.

139. The method of claim 138, further comprising, subsequent to the erasing, adding the block to a free list.

140. The method of claim 139, further comprising determining the third page of the less-fine-grained memory based, at least in part, on the free list.

141. The method of claim 119, further comprising, in event of a power disruption of a primary power source coupled to the fine-grained memory, powering the write buffer via a back-up power source.

142. The method of claim 141, further comprising, in the event of the power disruption being subsequent to the coalescing and prior to the writing, saving the particular page of the write buffer to a determined one of the pages of the less-fine-grained memory.

143. The method of claim 142, wherein the determined page of the less-fine-grained memory is the third page of the less-fine-grained memory.