Memory Security Device

• US 20080301467A1
• Filed: 05/28/2008
• Published: 12/04/2008
• Est. Priority Date: 05/31/2007
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Saito, Seiichiro
• Application Number:
  US12/128,322
• Publication Number:
  US 20080301467A1
• Time in Patent Office: Days
• US Class Current: 713/190
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2141 Access rights, e.g. capability lists, access control lists, access tables, access matrices
• CPC Class Codes: G06F 2221/2149 Restricted operating environment

Abstract

Embodiments of the systems and methods presented herein may provide memory security in a semiconductor device or a computing system using an address encryption section operable to encrypt a write address or a read address, a data encrypting section operable to encrypt data to be written, a write section operable to write encrypted data at an encrypted write address corresponding to a memory, a read section operable to read encrypted data from the encrypted read address corresponding to the memory and a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address.

Claims

1. A semiconductor device having a memory security block, the memory security block comprising:

an address encryption section operable to encrypt a write address or a read address;

a data encrypting section operable to encrypt data to be written;

a write section operable to write encrypted data at an encrypted write address corresponding to a memory;

a read section operable to read encrypted data from the encrypted read address corresponding to the memory; and

a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address.

2. The semiconductor device as recited in claim 1, further comprising:

a random number generating section; and

a random number storing section for storing a random number generated by the random number generating section, wherein the address encryption section encrypts the write address or the read address based on the stored random number, the data encryption section encrypts the data to be written based on the stored random number, and the date decryption section decrypts the read encrypted data based on the stored random number.

3. The semiconductor device as recited in claim 2, wherein

the address encryption section encrypts the write address by performing an operation between the write address and the stored random number and encrypts the read address by performing the operation between the read address and the stored random number,

the data encrypting section encrypts the data to be written by performing the operation between the data and the stored random number, and

the data decrypting section decrypts the read encrypted data by performing the operation between the read encrypted data and the stored random number.

4. The semiconductor device as recited in claim 3, wherein the operation is an exclusive OR (XOR).

5. The semiconductor device as recited in claim 1, further comprising:

a random number generating section; and

a random number storing section for storing a first random number and a second random number, wherein both the first random number and the second random number are generated by the random number generating section, the first random number and the second random number are distinct, the address encryption section encrypts the write address or the read address based on the stored first random number, the data encryption section encrypts the data to be written based on the stored second random number and the date decryption section decrypts the read encrypted data based on the stored second random number.

6. The semiconductor device as recited in claim 5, wherein the random number generates the first random number and the second random number when the memory security logic is activated or a reset instruction is received.

7. A method of protecting the contents of a memory, comprising:

if data is to be written;

encrypting a write address corresponding to a memory;

encrypting the data to be written; and

writing the encrypted data at the encrypted write address in the memory; and

if data is to be read;

encrypting a read address corresponding to the memory;

reading the encrypted data from the encrypted read address corresponding to the memory; and

decrypting the read encrypted data to obtain read data corresponding to the read address.

8. The method as recited in claim 7, further comprising:

generating a random number; and

storing the random number, wherein the write address and the read address is encrypted based on the stored random number, the write data is encrypted based on the stored random number, and the read encrypted data is decrypted based on the stored random number.

9. The method as recited in claim 8, wherein the write address is encrypted by performing an operation between the write address and the stored random number, the read address is encrypted by performing the operation between the read address and the stored random number, the data to be written is encrypted by performing the operation between the data and the stored random number, and read encrypted data is decrypted by performing the operation between the read encrypted data and the stored random number.

10. The method as recited in claim 9, wherein the operation is an exclusive OR (XOR).

11. The method as recited in claim 7, further comprising:

generating a first random number and a second number, wherein the first random number and the second random number are distinct; and

storing the first random number and the second random number, wherein the write address and the read address are encrypted based on the stored first random number, the write data is encrypted based on the stored second random number and the read encrypted data is decrypted based on the stored second random number.

12. The method as recited in claim 11, wherein the first random number and the second random number are generated when the memory security logic is activated or a reset instruction is received.

13. A computer system for use with digital television, comprising:

a multi-processor unit operable to decode compressed first data, generate second data from the first data and encode the second data to generate compressed second data;

a memory/processor controller operable to receive third data and store the third data in a first memory, the memory/processor controller having a memory security block, the memory security block comprising;

an address encryption section operable to encrypt a write address or a read address;

a data encrypting section operable to encrypt data to be written;

a write section operable to write encrypted data at an encrypted write address corresponding to the first memory;

a read section operable to read encrypted data from the encrypted read address corresponding to the first memory; and

a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address;

a central processing unit coupled to the memory/processor controller; and

an I/O unit coupled to one or more devices and operable to receive data from the one or more devices, a multi-processor unit and a memory/processor controller and communicate data to the one or more devices, the multi-processor unit and the memory/processor controller.

14. The computer system as recited in claim 13, wherein the first data is compressed in a first format and the second data is compressed in a second format different than the first format.

15. The computer system as recited in claim 14, wherein the second data is generated by editing the first data.

16. The computer system as recited in claim 14, wherein the second data is generated using a transcodec process

17. The computer system as recited in claim 13, wherein the computing system comprises a second memory and the multi-processor unit comprises a second memory security block comprising:

an address encryption section operable to encrypt a write address or a read address;

a data encrypting section operable to encrypt data to be written;

a write section operable to write encrypted data at an encrypted write address corresponding to the second memory;

a read section operable to read encrypted data from the encrypted read address corresponding to the memory; and

a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address.

18. The computer system as recited in claim 17, wherein the multi-processor unit comprises multiple processor elements and a control processor.

19. The computer system as recited in claim 18, wherein the multi-processor unit comprises a hardware decoder and a hardware encoder.

20. The computer system as recited in claim 13, wherein the one or more devices comprise a USB, an audio device, a network, a HDD, a DVD or a tuner.