Performance Analysis Based System Level Power Management

• US 20080301474A1
• Filed: 12/21/2006
• Published: 12/04/2008
• Est. Priority Date: 12/23/2005
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Bussa, Nagaraju, Dhand, Harsh, Srinivasan, Balakrishnan
• Application Number:
  US12/158,996
• Publication Number:
  US 20080301474A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiprocessor system-on-chip 102 with dynamic adaptive power management for execution of data-dependent applications comprises strategically placed performance counters to collect run-time performance requirements of tasks. A power manager 130 issues DVS 132, DFS 134, time-out 136, and other controls to the various system resources being monitored. As the tasks execute during run-time, the quality of the match between the task and the resource it was scheduled to is analyzed. More accurate power controls and schedules are then made available and stored in a performance requirements table. The power-management is therefore adaptive and dynamic. During a static analysis phase, applications and tasks that can be pre-characterized for their performance requirements are profiled and pre-loaded as initial starting points for correction during run-time.

Claims

1. A method of dynamic adaptive power management in multiprocessor system-on-chip comprising:

building a resource requirements table that tabulates tasks in an application program according to their performance requirements and resource power levels available in a multiprocessor system with power management controls, also the various operating voltages of the different cores and also the current running voltage level of the cores;

during a static phase, uploading resource requirements to said table;

during a dynamic phase, collecting information from a plurality of strategically placed performance counters, extracting dynamic performance requirements, and updating corresponding entries in said table;

consulting said table and using a power manager to set corresponding power levels to system resources scheduled for respective tasks.

2. The method of claim 1, wherein:

the consulting said table and using a power manager comprises selecting one of the cores operating at required power level or using at least one of DVS, DFS, and time-out, separately applied independently to one of said systems resources.

3. The method of claim 1, wherein:

the collecting information from a plurality of strategically placed performance counters is such that a performance counter is associated with each processor core, each peripheral, and an internal system bus to provide performance data.

4. The method of claim 1, wherein:

the uploading resource requirements to said table is such that said performance counters issue interrupts and are preloaded for known applications and uses, and the slack-times of each are computed to pre-estimate resource requirements.

5. A multiprocessor system-on-chip (SoC) with dynamic adaptive power management for execution of data-dependent applications, characterized by:

a plurality of performance counters with individual ones disposed in each processor each periphera, and an interconnecting internal system bus of a multiprocessor system implemented in a system-on-chip;

a resource requirements table that maps the performance levels required for a scheduled resource by a task in an application;

power manager for controlling at least one of DVS, DFS, and timeout to respective system resources associated with each of the performance counters, and that during run-time consults the resource requirements table for appropriate power management settings;

a static process for pre-loading the resource requirements table with performance requirements for a list of known applications and uses; and

a dynamic process for updating entries in the resource requirements table with performance requirements that have been extracted during run-time from data collected from the plurality performance c wherein, the power manager issues such controls as are necessary to optimize power at the system-level and such controls are dynamic and adaptive to changing conditions in the application that cannot be predicted before run-time.

6. The SoC of claim 5, further comprising:

a run-time profiler it for capturing the performance data from the performance counters and gives it to the performance prediction model, during run-time.

7. The SoC of claim 6, further comprising:

a performance requirements prediction model uses the data from the run-time profiler and predicts the performance requirements of the tasks.

8. The SoC of claim 5, further comprising:

a power manager for employing one of DVS, DFS, and time-out controls to individual system resources.

9. A prediction model for predicting the dynamic performance of application tasks that uses performance c and tabulates appropriate power requirements, and a power manager for dynamically using such tabulated information for on-line power management done at run-time, and such that the power management adapts to different input data and new applications while meeting each task'"'"'s performance requirements.