Method and apparatus for connecting multiple multimode processors

• US 20080301482A1
• Filed: 05/31/2007
• Published: 12/04/2008
• Est. Priority Date: 05/31/2007
• Status: Active Grant

• Current Assignee: Array Portfolio LLC
• Original Assignee: VNS Portfolio LLC
• Inventors: Goff, Lonnie C.
• Granted Patent: US 7,840,826 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A computer array 100 including a field of processors 101-124 each processor having a separate memory. The processors 101-124 are connected to their immediate neighbors with links 200. Several configurations of the links are described including differing types of data lines 210 and control lines 215. Along lines 215 Process Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors 101-124 to provide a method for altering the mode of hybrid processors 107-118 in the array.

Claims

1. A computer array comprised of a plurality of processors wherein each processor is connected to at least two adjoining processors by a link each link being connected to only two processors, and, wherein a plurality of said processors are switchable between a rest mode, and, an active mode upon receipt of an instruction on said link.

2. A computer array as in claim 1, wherein said link is further comprising a plurality of data lines.

3. A computer array as in claim 2, wherein said link is further comprising a plurality of control lines.

4. A computer array as in claim 3, wherein said control lines are unidirectional.

5. A computer array as in claim 1, wherein a plurality of processors at the edge of said array have three links connecting to three adjacent processors, and, four of said processors at each of the corners of said array have two associated links connecting to two of said processors at the edge of said array, and, a plurality of hybrid processors connected by four links to four processors, wherein the link of said edge processor not connected to a processor at the edge or corner of said array is connected to a single hybrid processor.

6. A computer array as in claim 5, wherein a plurality of processors at the corner of said array are adapted for connection to an external device selected from the group of memory, input devices, display devices and processing devices.

7. A computer array as in claim 5, wherein a plurality of processors at the edge of said array are adapted for connection to an external device selected from the group of memory, input devices, display devices and processing devices.

8. A computer array as in claim 5, wherein said hybrid processors switch between a routing mode, and, a processing mode, and, an idle mode upon receipt of an instruction from a link connected to said hybrid processor.

9. A computer array as in claim 8, wherein said each of links further comprise a data line, and, a control line, and, said instruction is a digital word passed over said data line.

10. A computer array as in claim 9, wherein said digital word is a routing word that causes said processor to switch into a routing mode.

11. A computer array as in claim 9, wherein said digital word is a processing word that causes said processor to switch into a processing mode.

12. A processor for use in a computer array comprising, a central processing unit adapted for connection to at least two links for connecting said processor to two immediately adjacent processors, and, a memory unit connected to said central processing unit, wherein an instruction on either of said links will cause said central processing unit to shift from an idle mode to an active mode.

13. A processor for use in a computer array as in claim 12, wherein said central procession unit is further adapted for connection to at least two additional links for connecting said processor to two additional immediately adjacent processors for a total of four links for connecting to four immediately adjacent processors.

14. A processor for use in a computer array as in claim 13, wherein said memory unit is further comprising a ROM memory and a RAM memory.

15. A processor for use in a computer array as in claim 13, wherein each of said links is further comprising a data line, and, a control line, and, said instruction is a digital word passed over said data line.

16. A processor for use in a computer array as in claim 15, wherein said control lines are unidirectional.

17. A processor for use in a computer array as in claim 12, wherein said central processing unit has three modes the first mode being an idle mode for conserving power, and, a second mode being a routing mode for performing routing tasks, and, a third mode being a processing mode for performing processing tasks, and, wherein switching the mode of said processing unit occurs upon receipt of an instruction over one of said links.

18. A processor for use in a computer array as in claim 12, wherein said central processing unit shifts from an idle mode to a routing mode upon receipt of a routing connection word and stays in the routing mode until the routing task is completed, and, then returns to the idle mode.

19. A processor for use in a computer array as in claim 12, wherein said central processing unit shifts from an idle mode to a processing mode upon receipt of a processing command word, and, stays in the routing mode until the processing task is completed, and, then returns to the idle mode.

20. A processor for use in a computer array as in claim 19, wherein said central processing unit shifts from an idle mode to a routing mode upon receipt of a routing connection word, and, stays in the routing mode until the routing task is completed, and, then returns to the idle mode.

21. A method for operating a multi processor array, comprising the steps of designating some of the processors in said array as multimode processors having at least an idle mode, and, an other mode for performing a task, switching said designated processors into said other mode upon receipt of a command word, and, performing a task upon receipt of said command word, and, switching back to idle mode upon completion of said task.

22. A method for operating a multi processor array as in claim 21, further comprising the steps of switching said designated processors into a routing mode upon receipt of a routing word, and, performing a routing task upon said receipt, and, returning to an idle mode upon completion of said routing task.