System and Method for Repairing a Memory

• US 20080301507A1
• Filed: 08/08/2008
• Published: 12/04/2008
• Est. Priority Date: 11/05/2003
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Virage Logic Corporation (Synopsys Incorporated)
• Inventors: Zorian, Yervant, Behera, Niranjan, Prickett, Bruce L. JR.
• Granted Patent: US 7,788,551 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.

Claims

1. A memory compiler for compiling at least one self-test and repair (STAR) memory instance, comprising:

a code portion for generating a built-in self-test and repair (BISTR) processor associated with said at least one STAR memory instance; and

a code portion for generating a test and repair wrapper operable to be integrated with input/output (I/O) circuitry of said at least one STAR memory instance to form a wrapper I/O (WIO) block, wherein said WIO block includes circuitry to generate a current error signal that is used locally by said BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion with respect to said STAR memory instance.

2. The memory compiler for compiling at least one STAR memory instance as set forth in claim 1, wherein said WIO block further includes circuitry for detecting that at least a portion of said STAR memory instance is faulty.

3. The memory compiler for compiling at least one STAR memory instance as set forth in claim 2, wherein said at least a portion of said STAR memory instance comprises a single I/O column.

4. The memory compiler for compiling at least one STAR memory instance as set forth in claim 2, wherein said at least a portion of said STAR memory instance comprises a plurality of I/O columns.

5. The memory compiler for compiling at least one STAR memory instance as set forth in claim 2, wherein said circuitry for detecting that at least a portion of said STAR memory instance is faulty comprises a read compare logic block operable to compare data output from said portion with a test compare data value.

6. The memory compiler for compiling at least one STAR memory instance as set forth in claim 5, wherein said read compare logic block is operable to generate an comparison error signal when said data output from said portion is different from said test compare data value.

7. The memory compiler for compiling at least one STAR memory instance as set forth in claim 6, wherein said comparison error signal is provided to a sticky scan flop for storing a fault information signal with respect to said faulty memory portion of said STAR memory instance.

8. The memory compiler for compiling at least one STAR memory instance as set forth in claim 6, wherein said comparison error signal is provided to a repair logic block for generating a REPAIR signal based on a RIPPLE signal and said repair enable control signal.

9. A memory instance having a plurality (N) of main array column (MAC) portions and a redundancy array column (RAC) portion, wherein each of said MAC portions and said RAC portion is associated with a sense amplifier and write driver (SAWD) circuit block for operably coupling with one of N input/output (I/O) blocks provided for said memory instance, said memory instance comprising:

means for detecting that one of said MAC portions is faulty;

means for decoupling said faulty MAC portion'"'"'s SAWD circuit block from an I/O block associated therewith and for shifting said faulty MAC portion'"'"'s I/O block to a SAWD circuit block associated with a MAC portion adjacent to said faulty MAC portion on a selected side thereof; and

means for successively shifting coupling relationships between SAWD circuit blocks and I/O blocks for each MAC portion disposed on said selected side of said faulty MAC portion until an I/O block associated with a MAC portion that is adjacent to said RAC portion is shifted to said RAC portion'"'"'s SAWD circuit block.

10. The memory instance as set forth in claim 9, wherein said means for detecting that one of said MAC portions is faulty is operable responsive to test information provided by a built-in self-test and repair (BISTR) processor associated with said memory instance.

11. The memory instance as set forth in claim 10, further comprising a test and repair logic wrapper into which said test information is scanned.

12. The memory instance as set forth in claim 9, wherein said means for successively shifting said coupling relationships between SAWD circuit blocks and I/O blocks is operable responsive to a RIPPLE control signal generated upon detecting that one of said MAC portions is faulty.

13. The memory instance as set forth in claim 9, wherein said means for detecting that one of said MAC portions is faulty comprises read compare logic operable to compare data output from said MAC portion with a test compare data value.

14. The memory instance as set forth in claim 13, wherein said read compare logic comprises an exclusive-OR circuit.

15. The memory instance as set forth in claim 9, wherein said means for decoupling and for shifting said faulty MAC portion'"'"'s I/O block comprises a multiplexer block operable responsive to a REPAIR signal.