TECHNIQUES FOR USE WITH AUTOMATED CIRCUIT DESIGN AND SIMULATIONS

• US 20080301601A1
• Filed: 05/08/2008
• Published: 12/04/2008
• Est. Priority Date: 05/09/2007
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Maixner, Richard C., Ng, Chun Kit, McElvain, Kenneth S., Larouche, Mario
• Granted Patent: US 8,756,557 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described.

Claims

1. A method comprising:

receiving initial condition signals from a circuitry in a chip; and

correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in a simulation, wherein the HDL was used in describing at least some of the circuitry in the chip.

2. The method of claim 1, wherein the circuitry includes a design logic and the initial condition signals are provided by a replicated logic in the circuitry.

3. The method of claim 2, wherein additional initial condition signals are received from another source.

4. The method of claim 1, wherein the circuitry includes a design memory and design registers and the initial condition signals are provided by a replicated memory and replicated registers in the circuitry.

5. The method of claim 1, further comprising prohibiting sequential optimization within a compiler software used to correlate an HDL design into netlists.

6. The method of claim 1, wherein formal verification flow techniques are used in correlating the initial condition signals.

7. The method of claim 1, wherein a portion of the circuitry is a replicated circuitry generated in part through hardware substitutions and the method further comprises correlating values of some of the initial condition signals by generating a list of hardware substitutions and using the list to trace back signal names and values from a physical implementation to HDL representations for the simulation.

8. The method of claim 7, wherein some of the hardware substitutions in the replicated circuitry include an original circuitry used with a control circuitry and a signal access circuitry to give access to states that are unexposed in the original circuitry.

9. The method of claim 7, wherein the original circuitry includes at least one of Xilinx SRL 16 shift registers and Altera Altshifttap shift registers.

10. The method of claim 1, wherein the circuitry provides the initial conditions in response to a trigger condition.

11. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to perform a method including:

receiving initial condition signals from a circuitry in a chip; and

correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in a simulation, wherein the HDL was used in describing at least some of the circuitry in the chip.

12. The apparatus of claim 11, wherein the circuitry includes a design logic and the initial condition signals are provided by a replicated logic in the circuitry.

13. The apparatus of claim 11, wherein the circuitry includes a design memory and design registers and the initial condition signals are provided by a replicated memory and replicated registers in the circuitry.

14. The apparatus of claim 11, wherein formal verification flow techniques are used in correlating the initial condition signals.

15. The apparatus of claim 11, wherein a portion of the circuitry is a replicated circuitry generated in part through hardware substitutions and the method further comprises correlating values of some of the initial condition signals by generating a list of hardware substitutions and using the list to trace back signal names and values from a physical implementation to HDL representations for the simulation.

16. The apparatus of claim 15, wherein some of the hardware substitutions in the replicated circuitry include an original circuitry used with a control circuitry and a signal access circuitry to give access to states that are unexposed in the original circuitry.

17. The apparatus of claim 11, wherein the circuitry provides the initial conditions in response to a trigger condition.

18. A method comprising:

receiving descriptions of a design circuitry;

selecting a portion of the design circuitry; and

replicating the selected portion of the circuitry,

wherein the replicated portion of the circuitry preserves the functionality and is different than the selected portion of the design circuitry for facilitating debugging or for simplifying the replicated circuitry.

19. The method of claim 18, wherein replicating the selected portion of the circuitry comprises prohibiting sequential optimization for ease of correlating data from the replicated portion of the circuitry with descriptions of the design circuitry.

20. The method of claim 18, wherein replicating the selected portion of the circuitry comprises generating in part through hardware substitutions, and wherein the hardware substitutions is documented for correlating data from the replicated portion of the circuitry with descriptions of the design circuitry.

21. The method of claim 18, wherein replicating the selected portion of the circuitry comprises adding an access circuitry to give access to states that are unexposed in the design circuitry.

22. The method of claim 18, wherein replicating the selected portion of the circuitry comprises adding a control circuitry to serially scan out the states of the replicated circuitry.

23. The method of claim 18, wherein replicating the selected portion of the design circuitry comprises substituting a functional equivalent replicated circuitry with access to states that are unexposed in the design circuitry.

24. The method of claim 18, wherein replicating the selected portion of the circuitry comprises omitting replicating an unknown logic module of the selected portion of the design circuitry and providing the outputs of the unknown logic module of the design circuitry as an input to the respective location within the replicated circuitry.

25. The method of claim 24, further comprising a delay logic between the outputs of the unknown logic module of the design circuitry and the input to the respective location within the replicated circuitry to account for the overall replicated logic delay.

26. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to perform a method including:

receiving descriptions of a design circuitry;

selecting a portion of the design circuitry; and

replicating the selected portion of the circuitry,

wherein the replicated portion of the circuitry preserves the functionality and is different than the selected portion of the design circuitry for facilitating debugging or for simplifying the replicated circuitry.

27. The apparatus of claim 26, wherein replicating the selected portion of the circuitry comprises prohibiting sequential optimization for ease of correlating data from the replicated portion of the circuitry with descriptions of the design circuitry.

28. The apparatus of claim 26, wherein replicating the selected portion of the circuitry comprises generating in part through hardware substitutions, and wherein the hardware substitutions is documented for correlating data from the replicated portion of the circuitry with descriptions of the design circuitry.

29. The apparatus of claim 26, wherein replicating the selected portion of the circuitry comprises adding an access circuitry to give access to states that are unexposed in the design circuitry.

30. The apparatus of claim 26, wherein replicating the selected portion of the circuitry comprises adding a control circuitry to serially scan out the states of the replicated circuitry.

31. The apparatus of claim 26, wherein replicating the selected portion of the design circuitry comprises substituting a functional equivalent replicated circuitry with access to states that are unexposed in the design circuitry.

32. The apparatus of claim 26, wherein replicating the selected portion of the circuitry comprises omitting replicating an unknown logic module of the selected portion of the design circuitry and providing the outputs of the unknown logic module of the design circuitry as an input to the respective location within the replicated circuitry.

33. The apparatus of claim 32, further comprising a delay logic between the outputs of the unknown logic module of the design circuitry and the input to the respective location within the replicated circuitry to account for the overall replicated logic delay.

34. A method comprising:

receiving descriptions of a circuitry including a design storage element; and

generating additional descriptions including descriptions of a replicated storage element, wherein the replicated storage element includes an original storage circuitry and an access circuitry to give access to states that are unexposed in the original storage circuitry.

35. The method of claim 34, wherein the design storage element and the replicated storage element each include a random access memory and the access circuitry allows reading out the memory content to an external device.

36. The method of claim 34, wherein the design storage element and the replicated storage element each include a proprietary logic module memory.

37. The method of claim 34, wherein the proprietary logic module memory is a shift register memory.

38. The method of claim 34, wherein the design storage element includes a proprietary logic module memory, and the replicated storage element includes an equivalent memory circuitry which is functional equivalent to the proprietary logic module memory.

39. The method of claim 34, wherein the design and replicated storage elements are in a single chip.

40. The method of claim 34, further comprising a control circuitry to serially scan out the content of the replicated storage element through the access circuitry.

41. The method of claim 34, wherein the additional descriptions include descriptions of an input signal storage circuitry to store the memory and register input signals and to provide at least some of the stored signals as input signals for a simulation.

42. The method of claim 41, wherein the input signal storage circuitry includes a first-in first-out circuitry.

43. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to:

receive descriptions of a circuitry including a design storage element; and

generate additional descriptions including descriptions of a replicated storage element as part of a hardware substitution, wherein the replicated storage element includes an original storage circuitry used with a control circuitry and a signal access circuitry to give access to states that are unexposed in the original storage circuitry.

44. The apparatus of claim 43, wherein the design storage element and the replicated storage element each include a random access memory and the access circuitry allows reading out the memory content to an external device.

45. The apparatus of claim 43, wherein the design storage element includes a proprietary logic module memory, and the replicated storage element includes an equivalent memory circuitry which is functional equivalent to the proprietary logic module memory.

46. The apparatus of claim 43, further comprising a control circuitry to serially scan out the content of the replicated storage element through the access circuitry.

47. The method of claim 43, further comprising an input signal storage circuitry to store the memory and register input signals and to provide at least some of the stored signals as input signals for a simulation.

48. The method of claim 47, wherein the input signal storage circuitry includes a first-in first-out circuitry.

49. A method comprising:

receiving descriptions of a circuitry including a design module including a first circuitry with some undescribed circuit details to provide signals to a design logic; and

generating additional descriptions including descriptions of a replicated module including a replicated logic that is a replication of the design logic, the replicated module omitting replicating the first circuitry, and a delay circuitry to receive output signals from the undescribed circuit of the first circuitry, wherein the output of the delay circuitry is provided to the corresponding locations in the replicated logic.

50. The method of claim 49, wherein the design module further includes an additional logic to provide signals to the first circuitry and wherein the replicated module includes an additional logic that is a replication of the additional logic in the design module.

51. The method of claim 49, further comprising a control circuitry to collect data from the replicated additional logic.

52. The method of claim 49, wherein the design and replicated modules are in a single chip.

53. The method of claim 49, wherein the design and replicated modules are in different chips.

54. The method of claim 49, wherein the additional descriptions include descriptions of an input signal storage circuitry to store the memory and register input signals and to provide at least some of the stored signals as input signals for a simulation.

55. The method of claim 54, wherein the input signal storage circuitry includes a first-in first-out circuitry.

56. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to:

receive descriptions of a circuitry including a design module including a first circuitry with some undescribed circuit details to provide signals to a design logic; and

generate additional descriptions including descriptions of a replicated module including a replicated logic that is a replication of the design logic, and a delay circuitry to receive output signals from the undescribed circuit of the first circuitry, wherein the output of the delay circuitry is provided to the corresponding locations in the replicated logic.

57. The apparatus of claim 56, wherein the design module further includes an additional logic to provide signals to the first circuitry and wherein the replicated module includes an additional logic that is a replication of the additional logic in the design module, and the delay circuitry includes a first-in first-out circuitry.

58. The apparatus of claim 56, further comprising a control circuitry to collect data from the replicated additional logic.

59. The apparatus of claim 56, further comprising an input signal storage circuitry to store the memory and register input signals and to provide at least some of the stored signals as input signals for the simulation.

60. The apparatus of claim 59, wherein the input signal storage circuitry includes a first-in first-out circuitry.

61. A method comprising:

receiving descriptions of a circuitry including a design circuitry; and

generating additional descriptions including descriptions of a replicated circuitry to be provided in a different chip than the design circuitry.

62. The method of claim 61, further comprising receiving descriptions of an additional circuitry including an additional design circuitry in at least one additional chip, and generating further additional descriptions including descriptions of an additional replicated circuitry to be provided in multiple chips that are different than the chips including the design circuitry.

63. The method of claim 61, wherein the design circuitry includes a design logic and the replicated circuitry includes a replicated logic to provide initial condition signals for a simulator.

64. The method of claim 61, wherein the design circuitry includes a design memory and design registers and the replicated circuitry includes a replicated memory and replicated registers to provide initial condition signals for a simulator.

65. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to:

receive descriptions of circuitry including a design circuitry; and

generate additional descriptions including descriptions of a replicated circuitry to be provided in a different chip than the design circuitry.

66. The apparatus of claim 65, further comprising receiving descriptions of an additional circuitry including an additional design circuitry in at least one additional chip, and generating further additional descriptions including descriptions of an additional replicated circuitry to be provided in multiple chips that are different than the chips including the design circuitry.

67. The apparatus of claim 65, wherein the design circuitry includes a design logic and the replicated circuitry includes a replicated logic to provide initial condition signals for a simulator.

68. The apparatus of claim 65, wherein the design circuitry includes a design memory and design registers and the replicated circuitry includes a replicated memory and replicated registers to provide initial condition signals for a simulator.