TECHNIQUES FOR USE WITH AUTOMATED CIRCUIT DESIGN AND SIMULATIONS
First Claim
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1. A method comprising:
- receiving initial condition signals from a circuitry in a chip; and
correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in a simulation, wherein the HDL was used in describing at least some of the circuitry in the chip.
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Abstract
Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described.
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Citations
68 Claims
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1. A method comprising:
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receiving initial condition signals from a circuitry in a chip; and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in a simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to perform a method including:
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receiving initial condition signals from a circuitry in a chip; and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in a simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method comprising:
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receiving descriptions of a design circuitry; selecting a portion of the design circuitry; and replicating the selected portion of the circuitry, wherein the replicated portion of the circuitry preserves the functionality and is different than the selected portion of the design circuitry for facilitating debugging or for simplifying the replicated circuitry. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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26. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to perform a method including:
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receiving descriptions of a design circuitry; selecting a portion of the design circuitry; and replicating the selected portion of the circuitry, wherein the replicated portion of the circuitry preserves the functionality and is different than the selected portion of the design circuitry for facilitating debugging or for simplifying the replicated circuitry. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33)
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34. A method comprising:
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receiving descriptions of a circuitry including a design storage element; and generating additional descriptions including descriptions of a replicated storage element, wherein the replicated storage element includes an original storage circuitry and an access circuitry to give access to states that are unexposed in the original storage circuitry. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
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43. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to:
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receive descriptions of a circuitry including a design storage element; and generate additional descriptions including descriptions of a replicated storage element as part of a hardware substitution, wherein the replicated storage element includes an original storage circuitry used with a control circuitry and a signal access circuitry to give access to states that are unexposed in the original storage circuitry. - View Dependent Claims (44, 45, 46, 47, 48)
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49. A method comprising:
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receiving descriptions of a circuitry including a design module including a first circuitry with some undescribed circuit details to provide signals to a design logic; and generating additional descriptions including descriptions of a replicated module including a replicated logic that is a replication of the design logic, the replicated module omitting replicating the first circuitry, and a delay circuitry to receive output signals from the undescribed circuit of the first circuitry, wherein the output of the delay circuitry is provided to the corresponding locations in the replicated logic. - View Dependent Claims (50, 51, 52, 53, 54, 55)
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56. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to:
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receive descriptions of a circuitry including a design module including a first circuitry with some undescribed circuit details to provide signals to a design logic; and generate additional descriptions including descriptions of a replicated module including a replicated logic that is a replication of the design logic, and a delay circuitry to receive output signals from the undescribed circuit of the first circuitry, wherein the output of the delay circuitry is provided to the corresponding locations in the replicated logic. - View Dependent Claims (57, 58, 59, 60)
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61. A method comprising:
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receiving descriptions of a circuitry including a design circuitry; and generating additional descriptions including descriptions of a replicated circuitry to be provided in a different chip than the design circuitry. - View Dependent Claims (62, 63, 64)
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65. An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to:
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receive descriptions of circuitry including a design circuitry; and generate additional descriptions including descriptions of a replicated circuitry to be provided in a different chip than the design circuitry. - View Dependent Claims (66, 67, 68)
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Specification