VENTED DIE AND PACKAGE

• US 20080303031A1
• Filed: 06/05/2008
• Published: 12/11/2008
• Est. Priority Date: 06/07/2007
• Status: Active Grant

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: United Test and Assembly Center Limited (UTAC Holdings Ltd.)
• Inventors: KOLAN, Ravi Kanth, TOH, Chin Hock, LIU, Hao
• Granted Patent: US 8,143,719 B2
• Time in Patent Office: Days
• US Class Current: 257/74
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/812 Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Claims

1. A die comprising:

a substrate having first and second major surfaces; and

at least one unfilled through via passing through the major surfaces of the substrate, wherein the unfilled via serves as a vent to release pressure generated during assembly.

2. The die of claim 1 comprises a plurality of through vias, the vias include conductive materials to form via contacts.

3. The die of claim 1 comprises die contacts at the first or second major surface.

4. The die of claim 1 comprises a through silicon via type die.

5. A chip package comprising:

a carrier having a first and second major surface, wherein the second major surface comprises a bonding region; and

a die attached to the bonding region, wherein the die includes

a substrate having first and second major surfaces, and

at least one unfilled through via passing through the major surfaces of the substrate, wherein the unfilled via serves as a vent to release pressure generated during assembly.

6. The chip package of claim 5 wherein the die comprises a through silicon via type die.

7. The chip package of claim 5 wherein the chip package includes more than one die forming a die stack.

8. The chip package of claim 7 wherein each die of the die stack comprises at least one unfilled via.

9. The chip package of claim 7 wherein the die stack includes a plurality of through vias, the vias include conductive materials to form via contacts.

10. The chip package of claim 7 wherein the top die of the die stack comprises a flip chip.

11. The chip package of claim 5 comprises an underfill material in a cavity in between the die and the carrier.

12. The chip package of claim 11 wherein the underfill material comprises material that includes max fillers, moldable underfills, epoxy mold compound or epoxy.

13. The chip package of claim 5 wherein the carrier further includes carrier vias.

14. The chip package of claim 5 comprises a package cap to encapsulate the die.

15. A method of chip packaging comprising:

providing a carrier having a bonding region on one of a top or bottom surface; and

attaching a die to the bonding region, wherein the die comprises at least one unfilled via through first and second major surfaces of the die to serve as a vent to release pressure generated during assembly.

16. The method of claim 15 wherein attaching the die comprises attaching a die stack comprising a plurality of dies, wherein at least one of the dies of the die stack comprises at least one unfilled via through first and second major surfaces of the die to serve as a vent to release pressure generated during assembly.

17. The method of claim 16 wherein each die of the die stack comprises at least one unfilled via to form a ventilation network for the die stack.

18. The method of claim 17 comprises forming a package cap encapsulating the die stack.

19. The method of claim 18 comprises filling the unfilled via of a top die of the die stack with insulating material.

20. The method of claim 16 comprises forming the die stack on top of a mother die, wherein the mother die includes an active die or a dummy interposer.