Non-volatile Memory Cells Including Fin Structures

• US 20080303079A1
• Filed: 08/18/2008
• Published: 12/11/2008
• Est. Priority Date: 05/31/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Choong-Ho, Cho, Eun-Suk, Kim, Tae-Yong
• Granted Patent: US 7,737,485 B2
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.

Claims

1. A non-volatile memory device comprising:

a fin protruding from a substrate;

a tunnel insulating layer on portions of the fin;

a floating gate on the tunnel insulting layer, so that the tunnel insulating layer is between the floating gate and the fin;

a dielectric layer on the floating gate, so that the floating gate is between the dielectric layer and the fin; and

a control gate electrode on the dielectric layer, so that the dielectric layer is between the control gate and the fin.

2. A non-volatile memory device according to claim 1 wherein the dielectric layer comprises a high-K dielectric material having a dielectric constant higher than a dielectric constant of silicon nitride.

3. A non-volatile memory device according to claim 2 wherein the high-K dielectric material includes at least one of hafnium oxide, aluminum oxide, and/or lanthanum oxide.

4. A non-volatile memory device according to claim 1 wherein the dielectric layer includes an aluminum oxide layer and at least one of a hafnium oxide layer and/or a lanthanum oxide layer.

5. A non-volatile memory device according to claim 1 wherein the fin has a mesa shape with a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate, wherein a transition from the mesa surface to a mesa sidewall has a rounded shape.

6. A non-volatile memory device according to claim 1 further comprising:

an insulating layer on the substrate adjacent the fin, wherein portions of the fin extend beyond the insulating layer, and wherein the insulating layer is between portions of the control gate electrode and the substrate.

7. A non-volatile memory device according to claim 1 wherein the control gate electrode comprises a conductive metal nitride layer in contact with the dielectric layer.

8. A non-volatile memory device according to claim 7 wherein the conductive metal nitride comprises at least one of titanium nitride, tantalum nitride, and/or tantalum nitride.

9. A non-volatile memory device according to claim 7 wherein the control gate electrode comprises a metal layer on the conductive metal nitride layer wherein the conductive metal nitride layer is between the metal layer and the dielectric layer.

10. A non-volatile memory device according to claim 9 wherein the metal layer comprises at least one of a tungsten layer and/or a molybdenum layer.

11. A non-volatile memory device according to claim 1 wherein portions of the fin extend beyond opposite sides of the control gate electrode wherein portions of the fin extending beyond the control gate electrode are doped.

12. A non-volatile memory device according to claim 1 further comprising:

a second fin protruding from the substrate wherein the first and second fins are parallel;

wherein the tunnel insulating layer is on portions of the first and second fins;

wherein the floating gate is on portions of the first and second fins with the tunnel insulating layer between the floating gate and the first and second fins;

wherein the dielectric layer is on the first and second fins with the floating gate between the dielectric layer and the first and second fins; and

wherein the control gate electrode crosses the first and second fins with the dielectric layer between the control gate electrode and the first and second fins.

13. A non-volatile memory device according to claim 12 further comprising:

first and second connection portions protruding from the substrate wherein the first connection portion is connected between the first and second fins on a first side of the control gate electrode, wherein the second connection portion is connected between the first and second fins on a second side of the control gate electrode.

14. A non-volatile memory device according to claim 12 wherein the first and second fins define a gap region therebetween.

15. A non-volatile memory device according to claim 14 further comprising:

an insulating layer on the substrate adjacent portions of the first and second fins, wherein portions of the first and second fins extend beyond the insulating layer, and wherein the insulating layer is between portions of the control gate electrode and the substrate.

16. A non-volatile memory device according to claim 15 wherein the gap region is free of the insulating layer.

17. A non-volatile memory device according to claim 16 wherein a surface of the substrate in the gap region is approximately level with a surface of the insulating layer.

18. A non-volatile memory device according to claim 14 wherein portions of the floating gate extend between the first and second fins in the gap region.

19. A non-volatile memory device according to claim 18 wherein the floating gate is conformal with respect to sidewalls of the first and second fins and portions of the substrate between the fins.

20. A non-volatile memory device according to claim 12 wherein portions of the first and second fins extend beyond opposite sides of the control gate electrode wherein portions of the fins extending beyond the control gate electrode are doped.

21. A non-volatile memory device according to claim 1 wherein the fin comprises semiconductor material.

22. A non-volatile memory device according to claim 1 wherein the fin and the substrate comprise a same semiconductor material and have a same crystal orientation.