BACK-SIDED TRAPPED NON-VOLATILE MEMORY DEVICE

• US 20080303080A1
• Filed: 07/22/2008
• Published: 12/11/2008
• Est. Priority Date: 06/21/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 7,851,827 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.

Claims

1. A back-side trap non-volatile memory cell, comprising:

a channel region;

a trap material; and

one or more sub-layers of dielectric material formed over the trap material and beneath the channel region;

wherein a conduction band offset of at least one of the one or more sub-layers of dielectric material is less than a conduction band offset of the trap material; and

wherein a conduction band offset of any one of the one or more sub-layers of dielectric material is less than a conduction band offset of any other sub-layer of dielectric material located between that one sub-layer of dielectric material and the trap material.

2. The memory cell of claim 1, further comprising:

a first and second source/drain region coupled by the channel region;

a charge blocking material formed beneath the trap material; and

a back-side gate formed beneath the charge blocking material.

3. The memory cell of claim 2, further comprising an access gate insulator formed over the channel region and an access gate formed over the access gate insulator.

4. The memory cell of claim 3, wherein the memory cell comprises a dual-gate non-volatile memory cell.

5. The memory cell of claim 2, wherein the charge blocking material comprises one of Al₂O₃, Pr₂O₃, and TiO₂.

6. The memory device of claim 2, wherein the back-side gate comprises one of polysilicon, tungsten, iridium, and aluminum.

7. The memory cell of claim 1, wherein the one or more sub-layers of dielectric material comprise one sub-layer of oxygen-rich SiON and the trap material comprises nitrogen-rich SiON.

8. The memory cell of claim 1, wherein the trap material is one of silicon oxynitride, nitrogen-rich silicon oxynitride, silicon nitride, silicon-rich silicon nitride, tantalum oxide, aluminum nitride and titanium oxide.

9. The memory cell of claim 8, wherein the trap material further comprises embedded nano-dots and/or nano-crystals.

10. The memory cell of claim 9 wherein the embedded nano-dots and/or nano-crystals comprise one of tungsten, silicon, germanium, cobalt, platinum, iridium, gold and palladium.

11. The memory cell of claim 1, wherein each of the one or more sub-layers is selected from a group of materials consisting of oxides, mixed oxides, nitrides, oxynitrides, mixed oxynitrides, silicates, SiO₂, SiN, Al₂O₃, Pr₂O₃, TiO₂, HfO₂, zirconium oxide, mixed oxide of hafnium and aluminum, mixed oxide of hafnium and titanium, mixed oxide of hafnium and silicon, SiON, AlN, and HfN.

12. A memory device, comprising:

a memory interface;

control circuitry coupled to the memory interface; and

an array of non-volatile memory cells, wherein one or more of the non-volatile memory cells comprises a back-side trap non-volatile memory cell each back-side trap non-volatile memory cell comprising;

a channel region;

a trap material having a conduction band offset; and

one or more sub-layers of dielectric material formed over the trap material and beneath the channel region, each sub-layer having a conduction band offset, wherein the conduction band offset of each of the one or more sub-layers is less than the trap material conduction band offset and wherein a conduction band offset of any one of the one or more sub-layers of dielectric material is less than a conduction band offset of any other sub-layer of dielectric material located between that one sub-layer of dielectric material and the trap material.

13. The memory device of claim 12, further comprising a charge blocking material formed beneath the trap material, a back-side gate formed beneath the charge blocking material, a first and a second source/drain region coupled by the channel region, a gate insulator formed over the channel region and an access gate formed over the gate insulator.

14. The memory device of claim 12, wherein the one or more sub-layers comprises a first sub-layer formed directly below the channel region and a second sub-layer formed directly below the first sub-layer wherein the conduction band offset of the first sub-layer is less than the conduction band offset of the second sub-layer.

15. The memory device of claim 12, wherein the memory device is included in a memory system, the memory system comprising the memory device coupled to a host.

16. A method of forming a back-side trap non-volatile memory cell, comprising:

forming a trapping material wherein the trapping layer has a conduction band offset;

forming one or more sub-layers of dielectric material on the trapping material, wherein each sub-layer of dielectric material has a conduction band offset and wherein the conduction band offset of each sub-layer of dielectric material is less than the conduction band offset of the material upon which it is formed; and

forming a channel region on the one or more sub-layers of dielectric material.

17. The method of claim 16, further comprising forming a first and a second source/drain region coupled by the channel region, forming a charge blocking material beneath the trapping material, and forming a back-side gate beneath the charge blocking material.

18. The method of claim 16, wherein forming one or more sub-layers of dielectric material further comprises forming a first sub-layer on the trapping material and forming a second sub-layer on the first sub-layer wherein the first sub-layer conduction band offset is greater than the second sub-layer conduction band offset.

19. The method of claim 18, wherein forming one or more sub-layers of dielectric material further comprises forming a third sub-layer directly on the second sub-layer wherein the second sub-layer conduction band offset e is greater than the third sub-layer band-gap value.

20. The method of claim 16, wherein each of the one or more sub-layers is selected from a group of materials consisting of oxides, mixed oxides, nitrides, oxynitrides, mixed oxynitrides.

21. A back-side trap non-volatile memory cell, comprising:

a channel region;

a trap material; and

an asymmetric band-gap tunnel dielectric comprising two or more sub-layers formed over the trap material and under the channel region, wherein each sub-layer has an increasing conduction band offset extending from the channel region to the trap material.

22. The memory cell of claim 21, wherein the two or more sub-layers comprises a first sub-layer formed under the channel region and a second sub-layer formed under the first sub-layer, wherein the first sub-layer conduction band offset is less than the second sub-layer conduction band offset.

23. The memory cell of claim 22, further comprising a third sub-layer formed under the second sub-layer wherein the second sub-layer conduction band offset is less than the third sub-layer conduction band offset.

24. The memory cell of claim 23, wherein the first sub-layer, the second sub-layer and the third sub-layer each have an associated dielectric constant value, wherein the second sub-layer dielectric constant is greater than the first sub-layer dielectric constant, and wherein the third sub-layer dielectric constant is greater than the second sub-layer dielectric constant.