ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER

• US 20080303564A1
• Filed: 08/20/2008
• Published: 12/11/2008
• Est. Priority Date: 04/18/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Feng, Kai Di
• Granted Patent: US 8,122,395 B2
• Time in Patent Office: Days
• US Class Current: 327/153
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

Claims

1. A receiver circuit comprising:

a plurality of channels; and

a configuration word interface connected to said channels, wherein each of said channels comprises adjustable delay circuitry,

wherein said configuration word interface controls said adjustable delay circuitry to coordinate a signal timing of all of said channels.

2. The receiver circuit in claim 1, wherein said adjustable delay circuitry further comprises programmable delay units and delay registers connected between said programmable delay units and said configuration word interface.

3. The receiver circuit in claim 2, wherein said delay registers are adapted to store information regarding an individual timing delay of an associated programmable delay unit.

4. The receiver circuit in claim 1, wherein said configuration word interface is connected to an external controller that supplies information to control said adjustable delay circuitry.

5. The receiver circuit in claim 1, wherein said adjustable delay circuitry and said configuration word interface are positioned on a single printed circuit board.

6. The receiver circuit in claim 1, wherein said configuration word interface permits dynamic control of adjustable delay circuitry so that said signal timing of said all of said channels is the same.

7. The receiver circuit in claim 1, wherein said configuration word interface includes a phase voltage converter.

8. A receiver circuit comprising:

a plurality of channels; and

a configuration word interface connected to said channels, wherein each of said channels comprises adjustable delay circuitry comprising at least one programmable delay unit,

wherein said configuration word interface controls said adjustable delay circuitry to coordinate signal timing of all of said channels.

9. The receiver circuit in claim 8, wherein said adjustable delay circuitry further comprises at least one delay register connected between said at least one programmable delay unit and said configuration word interface.

10. The receiver circuit in claim 9, wherein said at least one delay register is adapted to store information regarding individual timing delay of said at least one programmable delay unit.

11. The receiver circuit in claim 8, wherein said configuration word interface is connected to an external controller that supplies information to control said adjustable delay circuitry.

12. The receiver circuit in claim 8, wherein said adjustable delay circuitry and said configuration word interface are positioned on a single printed circuit board.

13. The receiver circuit in claim 8, wherein said configuration word interface permits dynamic control of said adjustable delay circuitry so that said signal timing of said all of said channels is the same.

14. The receiver circuit in claim 8, wherein said configuration word interface includes a phase voltage converter.

15. A receiver circuit comprising:

a plurality of channels; and

a configuration word interface connected to said channels, wherein each of said channels comprises adjustable delay circuitry comprising a first programmable delay unit for input bit signal delay and a second programmable delay unit for clock delay,

wherein said configuration word interface controls said adjustable delay circuitry to adjust delay times of at least some of said channels so that signal timing of all of said channels is the same.

16. The receiver circuit in claim 15, wherein said adjustable delay circuitry further comprises:

a first delay register connected between said first programmable delay unit and said configuration word interface, wherein said first delay register is adapted to store information regarding timing delay of said first programmable delay unit.

17. The receiver circuit in claim 16, wherein said adjustable delay circuitry further comprises:

a second delay register connected between said second programmable delay unit and said configuration word interface, wherein said second delay register is adapted to store information regarding timing delay of said second programmable delay unit.

18. The receiver circuit in claim 15, wherein at least one of said first programmable delay unit and said second programmable delay unit comprise:

a resistor-capacitor network;

a Schmitt trigger connected to said resistor-capacitor network; and

a digital-to-analog converter connected to said resistor-capacitor network.

19. The receiver circuit in claim 15, wherein at least one of said first programmable delay unit and said second programmable delay unit comprise:

a resistor-capacitor network;

variable transistors connected to said resistor-capacitor network; and

a digital-to-analog converter connected to said resistor-capacitor network.