SOLID STATE MEMORY UTILIZING ANALOG COMMUNICATION OF DATA VALUES

• US 20080304317A1
• Filed: 06/05/2007
• Published: 12/11/2008
• Est. Priority Date: 06/05/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,719,901 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. This analog signal may then be processed to convert it to a digital representation of the individual bits of the bit pattern represented by the analog signal. Such memory devices may be incorporated into bulk storage devices, and may utilize form factors and communication protocols of hard disk drives (HDDs) and other traditional bulk storage devices for transparent replacement of such traditional bulk storage devices in electronic systems.

Claims

1. A solid state memory device, comprising:

an array of non-volatile memory cells;

circuitry for control and/or access of the array of non-volatile memory cells;

wherein the circuitry for control and/or access is adapted to generate an analog data signal indicative of a threshold voltage of a target memory cell of the array.

2. The solid state memory device of claim 1, wherein the circuitry for control and/or access of the array of non-volatile memory cells comprises circuitry to sample and hold a voltage level indicative of the threshold voltage of the target memory cell and to generate the analog data signal from the held voltage level.

3. The solid state memory device of claim 2, wherein the circuitry to sample and hold a voltage level indicative of the threshold voltage of the target memory cell is adapted to amplify and/or buffer the held voltage level in generating the analog data signal.

4. The solid state memory device of claim 2, wherein the circuitry to sample and hold a voltage level indicative of the threshold voltage of the target memory cell comprises one or more capacitors to hold the voltage level indicative of the threshold voltage of the target memory cell.

5. The solid state memory device of claim 1, wherein the circuitry for control and/or access of the array of non-volatile memory cells is further adapted to convert the generated analog data signal to two or more digital data signals for output from the memory device.

6. The solid state memory device of claim 5, wherein the circuitry for control and/or access of the array of non-volatile memory cells is further adapted to receive digital data signals and to convert two or more of the digital data signals to an analog data signal indicative of a desired threshold voltage of the target memory cell.

7. The solid state memory device of claim 6, wherein the circuitry for control and/or access of the array of non-volatile memory cells is further adapted to store a voltage level of the analog data signal indicative of the desired threshold voltage of the target memory cell, to compare the threshold voltage of the target memory cell to the stored voltage level, and to increase the threshold voltage of the target memory cell if it is found to be less than the stored voltage level.

8. The solid state memory device of claim 1, wherein the circuitry for control and/or access of the array of non-volatile memory cells is further adapted to receive an analog data signal indicative of a desired threshold voltage of the target memory cell.

9. The solid state memory device of claim 8, wherein the circuitry for control and/or access of the array of non-volatile memory cells is further adapted to store a voltage level of the analog data signal indicative of the desired threshold voltage of the target memory cell, to compare the threshold voltage of the target memory cell to the stored voltage level, and to increase the threshold voltage of the target memory cell if it is found to be less than the stored voltage level.

10. A solid state memory device, comprising:

an NAND memory array; and

circuitry for control and/or access of non-volatile memory cells of the NAND memory array;

wherein the circuitry for control and/or access of the non-volatile memory cells comprises circuitry to sample a voltage indicative of a threshold voltage of a target memory cell and to store the sampled voltage for transfer to an external device.

11. The solid state memory device of claim 10, wherein the circuitry for control and/or access of the non-volatile memory cells is adapted to amplify and/or buffer the stored voltage prior to transferring to the external device.

12. The solid state memory device of claim 10, wherein the circuitry to store the sampled voltage comprises one or more capacitors.

13. The solid state memory device of claim 10, wherein the circuitry for control and/or access of the non-volatile memory cells is adapted to receive an analog data signal indicative of a desired threshold voltage of the target memory cell.

14. The solid state memory device of claim 13, wherein the circuitry for control and/or access of the non-volatile memory cells is adapted to store a voltage of the analog data signal indicative of the desired threshold voltage of the target memory cell, to compare the threshold voltage of the target memory cell to the stored voltage indicative of the desired threshold voltage of the target memory cell, and to increase the threshold voltage of the target memory cell if it is found to be less than the stored voltage indicative of the desired threshold voltage of the target memory cell.

15. A bulk storage device, comprising:

a solid state memory device adapted to receive and transmit analog data signals indicative of data values of two or more bits of information;

a controller for communicating with an external device; and

a read/write channel coupled to the controller and the memory device;

wherein the read/write channel is adapted to convert analog data signals received from the memory device to digital data signals for transmission to the controller; and

wherein the read/write channel is adapted to convert digital data signals received from the controller to analog data signals for transmission to the memory device.

16. The bulk storage device of claim 15, wherein the memory device is further adapted to store voltage levels indicative of received analog data signals in a write operation and to program target memory cells of the write operation until their threshold voltages equal or exceed the stored voltage levels.

17. The bulk storage device of claim 15, wherein the memory device is further adapted to generate analog data signals for transmission having voltage levels indicative of threshold voltages of target memory cells corresponding to each analog data signal.

18. The bulk storage device of claim 17, wherein the read/write channel is further adapted to receive the analog data signals from the memory device as a stream of analog data signals, to perform signal processing to generate a digital representation of the stream of analog data signals, and to determine from the digital representation a likely pattern of threshold voltages responsible for generating the stream of analog data signals.

19. The bulk storage device of claim 18, wherein the read/write channel is further adapted to generate digital data signals corresponding to bit patterns represented by the likely pattern of threshold voltages.

20. The bulk storage device of claim 19, wherein the read/write channel is further adapted to apply error correction prior to generating the digital data signals corresponding to bit patterns represented by the likely pattern of threshold voltages.

21. The bulk storage device of claim 15, wherein the bulk storage device comprises a form factor and a communication protocol in use for hard disk drives.

22. The bulk storage device of claim 15, wherein the controller and the read/write channel are parts of a single integrated circuit device.

23. A bulk storage device, comprising:

a solid state memory device adapted to process and generate analog data signals indicative of data values of two or more bits of information; and

a controller for communicating with an external device;

wherein the solid state memory device is further adapted to receive digital data signals from the controller and to provide digital-to-analog conversion to convert two or more of the digital data signals to an analog data signal for writing to a memory array of the memory device; and

wherein the solid state memory device is further adapted to provide analog-to-digital conversion to convert an analog data signal read from the memory array of the memory device to two or more digital data signals for output to the controller.

24. The bulk storage device of claim 23, wherein the memory device is further adapted to store voltage levels indicative of converted digital data signals in a write operation and to program target memory cells of the write operation until their threshold voltages equal or exceed the stored voltage levels.

25. The bulk storage device of claim 23, wherein the memory device is further adapted to generate analog data signals during a read operation indicative of threshold voltages of target memory cells corresponding to each analog data signal.

26. The bulk storage device of claim 23, wherein the bulk storage device comprises a form factor and a communication protocol in use for hard disk drives.

27. A method of writing data to a memory device having an array of non-volatile memory cells, comprising:

storing an analog data signal at the memory device;

applying programming pulses to a target memory cell to increase a threshold voltage of the target memory cell;

comparing the threshold voltage of the target memory cell to the stored analog data signal; and

re-applying programming pulses to the target memory cell if its threshold voltage is less than a voltage level of the stored analog data signal.

28. The method of claim 27, wherein comparing the threshold voltage of the target memory cell to the stored analog data signal comprises comparing the threshold voltage of the target memory cell to the stored analog data signal using a differential amplifier.

29. The method of claim 27, further comprising continuing to apply programming pulses to the target memory cell until its threshold voltage equals or exceeds the voltage level of the stored analog data signal.

30. The method of claim 27, further comprising:

receiving an analog data signal indicative of a desired threshold voltage of the target memory cell prior to storing the analog data signal at the memory device.

31. The method of claim 27, further comprising:

receiving two or more digital data signals indicative of a bit pattern to be stored on the target memory cell; and

converting the two or more digital data signals to an analog data signal indicative of a desired threshold voltage of the target memory cell prior to storing the analog data signal at the memory device.

32. A method of reading data from a memory device having an array of non-volatile memory cells, comprising:

generating a voltage level indicative of a threshold voltage of a target memory cell;

sampling the voltage level indicative of the threshold voltage of the target memory cell; and

generating an analog data signal indicative of the sampled voltage level indicative of the threshold voltage of the target memory cell.

33. The method of claim 32, wherein generating a voltage level indicative of a threshold voltage of a target memory cell comprises generating a voltage level substantially equal to the threshold voltage of a target memory cell.

34. The method of claim 32, further comprising:

transmitting the analog data signal indicative of the sampled voltage level from the memory device.

35. The method of claim 34, wherein transmitting the analog data signal indicative of the sampled voltage level occurs in parallel with analog data signals indicative of threshold voltages of other memory cells.

36. The method of claim 34, wherein transmitting an analog data signal indicative of the sampled voltage level occurs in serial with analog data signals indicative of threshold voltages of other memory cells.

37. The method of claim 32, further comprising:

generating two or more digital data signals corresponding to a data bit pattern represented by the analog data signal; and

transmitting the digital data signals to a host processor.

38. The method of claim 32, further comprising:

receiving a stream of analog data signals indicative of threshold voltages of a plurality of memory cells;

generating a digital representation of the stream of analog data signals; and

determining a likely pattern of threshold voltages of the memory cells responsible for generating the stream of analog data signals.

39. The method of claim 38, further comprising:

generating digital data signals corresponding to data bit patterns of the likely pattern of threshold voltages; and

transmitting the digital data signals to a host processor.