NAND FLASH MEMORY CELL PROGRAMMING
First Claim
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1. A method of protecting data integrity in a non-volatile memory cell, comprising:
- transferring a first voltage to a word line conductor at a level sufficient to reduce a snap-back condition;
placing an intermediate voltage on a global word line conductor for coupling to the word line conductor;
placing a second voltage on a bit line conductor if a driver signal exceeds the second voltage by at least a threshold voltage and the second voltage exceeds the intermediate voltage on the global word line conductor;
coupling the word line conductor to a gate of a non-volatile memory cell.
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Abstract
A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are described.
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Citations
22 Claims
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1. A method of protecting data integrity in a non-volatile memory cell, comprising:
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transferring a first voltage to a word line conductor at a level sufficient to reduce a snap-back condition; placing an intermediate voltage on a global word line conductor for coupling to the word line conductor; placing a second voltage on a bit line conductor if a driver signal exceeds the second voltage by at least a threshold voltage and the second voltage exceeds the intermediate voltage on the global word line conductor; coupling the word line conductor to a gate of a non-volatile memory cell. - View Dependent Claims (2, 3, 4, 5)
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6. A method of protecting data integrity in a non-volatile memory cell, comprising:
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applying a first voltage to word line conductors coupled to a selected block of transistors; isolating the word line conductors from global word line conductors after applying the first voltage; applying a second voltage to the global word line conductors, the second voltage greater than the first voltage; passing the second voltage to the selected block of transistors; selectively coupling a third voltage to at lease one transistor of the selected block of transistors to program a bit, the third voltage greater than the second voltage; and coupling each word line conductor to an individual gate of a non-volatile memory cell. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A method of protecting data integrity in a non-volatile memory array, comprising:
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coupling a first voltage to first word line conductors associated with at least one of selected and unselected memory cells; coupling a second voltage to second word line conductors of the unselected memory cells, the second voltage greater than the first voltage; coupling a third voltage to a third world line conductor of the selected memory cells, the third voltage greater than the second; discharging at least one of the first, second and third word line conductors; and coupling the first, second and third word line conductors to a respective set of gates of a non-volatile memory cell in a memory array. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification