Logic verification system

• US 20080306722A1
• Filed: 02/08/2008
• Published: 12/11/2008
• Est. Priority Date: 10/17/2002
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamagiwa, Akira, Nanao, Hisashi, Fujii, Mototsugu, Tada, Osamu, Morimoto, Kazunobu
• Application Number:
  US12/068,628
• Publication Number:
  US 20080306722A1
• Time in Patent Office: Days
• US Class Current: 703/15
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge circuit used in the verification processes of a logic simulator accelerator and a logic emulator, a cutting end of the verification object logic is assigned to an external interface connector of the FPGA module when the logic simulation is accelerated, and the correspondence between each pin of external interface connector of the FPGA module and logic signal is performed on the logic simulator on the general purpose processor.

Claims

1. A logic verification system comprising:

a logic simulation accelerator including;

a logic simulator operating on a general purpose processor to logically verify operation correctness of a designed logic circuit;

a device which includes a programmable FPGA module composed by FPGAs to be programmed to physically realize functions of the designed logic circuit and which is mounted to the logic simulator via a connector; and

a bridge circuit which is mounted to the logic simulator and which selectively transmits and receives corresponding data between said general purpose processor and said device,

wherein all pins of the FPGA module are wired directly to the bridge circuit via the connector,

wherein a cutting end of a verification logic which verifies said designed logic circuit realized on said device is assigned to the connector of the FPGA module for accelerating logic simulation, and

wherein a correspondence between each of said all pins of said FPGA module and a logic signal from said general purpose processor is established on said logic simulator, and

wherein the verification logic for verifying said designed logic circuit implemented on said device provides a means for transmitting a direction control signal which controls a transmission direction of two-way signals between said FPGA module and said bridge circuit thereby performing logic verification of the designed logic circuit by the logic simulator in parallel with physical realization of the designed logic circuit on said device, and said direction control signal is sent to the bridge circuit via one of said two-way signals.

2. The logic verification system according to claim 1, further comprising a means for automatically detecting a signal direction of a two-way signal between said FPGA module and the bridge circuit, and program data of the same FPGA module implementing different verification logics is used in verification processes consisting of acceleration of logic simulation and logic emulation for a plurality of designed logic circuits.

3. The logic verification system according to claim 2, wherein said means for automatically detecting the signal direction of the two-way signal sets a drivability level of output circuits of the FPGA module and the bridge circuit, and gives priority in determination of signal direction to one of the FPGA module and the bridge circuit which has a higher drivability.

4. The logic verification system according to claim 2, further comprising:

a means for inputting the signal direction of the two-way signal to the logic simulator on the general purpose processor,

wherein a disagreement between the signal direction of the two-way signal to the logic simulator and a signal direction indicted in said direction control signal is detected by comparing said signal directions.

5. The logic verification system according to claim 4, wherein said means for automatically detecting the signal direction of the two-way signal sets a drivability level of output circuits of the FPGA module and the bridge circuit, and gives priority in determination of signal direction to one of the FPGA module and the bridge circuit which has a higher drivability.

6. The logic verification system according to claim 1, wherein said direction control signal is added into the verification logic.

7. The logic verification system according to claim 1, wherein said direction control signal is instead transmitted on a time division basis with said two-way signals.

8. The logic verification system according to claim 1, wherein said FPGAs are connected via switching devices to the bridge circuit.

9. The logic verification system according to claim 1, wherein the bridge circuit is realized with at least one of the FPGAs.