Emulated Combination Memory Device

• US 20080306723A1
• Filed: 05/23/2008
• Published: 12/11/2008
• Est. Priority Date: 06/08/2007
• Status: Abandoned Application

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Dietrich, Stefan, Schroegmeier, Peter, De Ambroggi, Luca, Redaelli, Marco
• Application Number:
  US12/126,738
• Publication Number:
  US 20080306723A1
• Time in Patent Office: Days
• US Class Current: 703/21
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.

Claims

1. An integrated circuit memory device comprising:

a non-volatile memory array comprising a first emulated memory region and a second emulated memory region; and

a controller coupled to the array, the controller having a first interface;

wherein the memory device is configured to emulate a first emulated memory type and a second emulated memory type, and wherein the memory device is configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.

2. The memory device of claim 1, wherein the first emulated memory type is a non-volatile memory type and the second emulated memory type is a volatile memory type.

3. The memory device of claim 2, wherein the first emulated memory type is NOR flash memory.

4. The memory device of claim 2, wherein the second emulated memory type is pseudo-static random access memory (PSRAM).

5. The memory device of claim 1, wherein the first interface is configured to provide access to both the first emulated memory type and the second emulated memory type.

6. The memory device of claim 5, further comprising a selector, configured to select whether to emulate the first emulated memory type or the second emulated memory type.

7. The memory device of claim 6, wherein the selector is configured to determine whether to emulate the first emulated memory type or the second emulated memory type based at least in part on a memory address to be accessed.

8. The memory device of claim 6, wherein the selector is configured to determine whether to emulate the first emulated memory type or the second emulated memory type based at least in part on contents of a configuration register.

9. The memory device of claim 1, wherein the controller comprises a first control portion that controls emulation of the first emulated memory type and a second control portion that controls emulation of the second emulated memory type.

10. The memory device of claim 9, wherein the controller further comprises a second interface, and wherein the first interface is associated with the first control portion, and the second interface is associated with the second control portion.

11. The memory device of claim 10, wherein the first interface comprises a first chip enable line that enables the first control portion, and the second interface comprises a second chip enable line that enables the second control portion.

12. The memory device of claim 9, wherein the controller further comprises a shared interface, comprising one or more lines that are shared by both the both the first control portion and the second control portion.

13. The memory device of claim 1, wherein the memory device emulates a timing of the first emulated memory type and a timing of the second emulated memory type.

14. The memory device of claim 1, wherein the memory device uses an emulated refresh cycle of a volatile memory type to conceal a latency time for writing data to the non-volatile memory array.

15. The memory device of claim 1, wherein the non-volatile memory array comprises phase changing random access memory (PCRAM).

16. A method of providing access to multiple memory types within a single integrated circuit memory device, the method comprising:

providing a non-volatile memory array comprising a first emulated memory region and a second emulated memory region;

configuring the memory device to emulate a first memory type and a second memory type;

storing data in the first emulated memory region when the memory device emulates the first memory type; and

storing data in the second emulated memory region when the memory device emulates the second emulated memory type.

17. The method of claim 16, wherein configuring the memory device to emulate a first memory type and a second memory type comprises:

configuring the memory device to emulate a non-volatile memory type; and

configuring the memory device to emulate a volatile memory type.

18. The method of claim 17, wherein configuring the memory device to emulate a non-volatile memory type comprises configuring the memory device to emulate a NOR flash memory.

19. The method of claim 17, wherein configuring the memory device to emulate a volatile memory type comprises configuring the memory device to emulate a pseudo-static random access memory (PSRAM).

20. The method of claim 16, wherein configuring the memory device to emulate a first memory type and a second memory type comprises providing a single interface to the first emulated memory type and the second emulated memory type.

21. The method of claim 20, further comprising providing a selector configured to determine whether to emulate the first memory type or the second memory type.

22. The method of claim 21, wherein providing a selector comprises providing a selector configured to determine whether to emulate the first memory type or the second memory type depending at least in part on a memory address.

23. The method of claim 21, wherein providing a selector comprises providing a selector configured to determine whether to emulate the first memory type or the second memory type depending at least in part on the contents of a configuration register.

24. The method of claim 16, wherein configuring the memory device to emulate a first memory type and a second memory type comprises providing a first interface to the first memory type and providing a second interface to the second memory type.

25. The method of claim 24, wherein providing a first interface to the first memory type comprises providing a first chip select line that selects emulation of the first memory type, and wherein providing a second interface to the second memory type comprises providing a second chip select line that selects emulation of the second memory type.

26. The method of claim 16, wherein configuring the memory device to emulate a first memory type and a second memory type comprises configuring the memory device to emulate a timing of the first emulated memory type and a timing of the second emulated memory type.

27. The method of claim 16, wherein configuring the memory device to emulate a first memory type and a second memory type comprises configuring the memory device to emulate a volatile memory type, and the method further comprises using an emulated refresh cycle of the volatile memory type to conceal a latency time for writing data to the non-volatile memory array.

28. The method of claim 16, wherein providing a non-volatile memory array comprises providing a phase changing random access memory (PCRAM) array.

29. A memory device comprising:

a phase changing random access memory (PCRAM) array;

a controller;

a first chip enable line coupled to the controller and configured to enable emulation of a flash memory; and

a second chip enable line coupled to the controller and configured to enable emulation of a pseudo-static random access memory (PSRAM);

wherein the memory device is configured to store data in a first area of the PCRAM array when the first chip enable line is set, and to store data in a second area of the PCRAM array when the second chip enable line is set.