Expanded Memory for Communications Controller

• US 20080307132A1
• Filed: 06/05/2007
• Published: 12/11/2008
• Est. Priority Date: 06/05/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Zaks, Artur, Gurewitz, Oran
• Granted Patent: US 7,627,700 B2
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and reception of communications data in a network. The system also comprises a memory configured to store configuration data associated with fee communications controller and application parameters associated with each of a plurality of communications applications. The system further comprises art interface converter interconnecting the communications controller and the memory and configured to convert a first bus interlace protocol associated with fee communications controller to a second bus interface protocol for providing read and write data transfer of fee configuration data and the application parameters between the communications controller and the memory.

Claims

1. A communication system comprising:

a communications controller configured to control transmission and reception of communications data in a network;

a memory configured to store configuration data associated with the communications controller and application parameters associated with each of a plurality of communications applications; and

an interface converter interconnecting the communications controller and the memory and configured to convert a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read and write data transfer of the configuration data and the application parameters between the communications controller and the memory.

2. The system of claim 1, wherein the first bus interface protocol is inter-integrated circuit (I²C) protocol.

3. The system of claim 1, wherein the memory comprises a flash memory.

4. The system of claim 1, wherein the read and write data transfer comprises a burst read data transfer and a burst write data transfer of a plurality of consecutive data blocks associated with the configuration data and application parameters between the communications controller and the memory via the interface converter.

5. The system of claim 4, wherein the communications controller comprises a local memory, the burst read data transfer comprising the plurality of consecutive data blocks being transmitted from the first memory to the local memory, such that consecutive address registers in the local memory are overwritten by the plurality of consecutive data blocks.

6. The system of claim 4, wherein the interface converter is further configured to provide an interrupt signal to the communications controller to indicate a completion of at least one of the burst read data transfer and the burst write data transfer.

7. The system of claim 4, wherein the communications controller comprises a timer having a preset corresponding to an estimated time of completion of at least one of the burst read data transfer and the burst write data transfer, and wherein the communications controller is further configured to write a predefined data pattern in an end address of consecutive address registers in an address space associated with the one of the communications controller and the memory to which the plurality of consecutive data blocks are transferred.

8. The system of claim 7, wherein the communications controller, upon expiration of the preset, determines if the predefined data pattern has been written over to signify a completion of the at least one of the burst read data transfer and the burst write data transfer, and wherein the communications controller sets the preset for a longer estimated time upon the predefined data pattern having not been written over.

9. A network communications device comprising the system of claim 1.

10. A method for communicating with a memory device, the method comprising:

transmitting a plurality of consecutive data blocks from a communications controller on a first data bus via inter-integrated circuit (I²C) protocol;

converting the I²C protocol to a second bus interface protocol for transmission of the plurality of consecutive data blocks on a second data bus; and

storing the plurality of consecutive data blocks in the memory device via the second data bus.

11. The method of claim 10, wherein transmitting the plurality of consecutive data blocks comprises transmitting application parameters associated with a respective one of a plurality of communications applications corresponding to one of transmission and reception of communications data via the communications controller.

12. The method of claim 10, further comprising generating an interrupt signal to the communications controller to indicate a completion of the transmission, of the plurality of consecutive data blocks from the communications controller.

13. The method of claim 10, further comprising:

writing a predefined data pattern at an end address register of a plurality of address registers in the memory device;

setting a preset time associated with a timer corresponding to an estimated time of completion of the transmission of the plurality of consecutive data blocks from the communications controller;

incrementing the timer; and

monitoring the end address register in the memory device upon the timer reaching the preset time to indicate a completion of the transmission of the plurality of consecutive data blocks from the communications controller.

14. The method of claim 13, further comprising increasing the preset time upon the address register in the memory device storing the predefined data pattern upon monitoring the address register in the memory device.

15. The method of claim 10, further comprising:

transmitting a second plurality of consecutive data blocks from the memory device on the second data bus via the second bus interface protocol;

converting the second bus interface protocol to the I²C protocol for transmission of the second plurality of consecutive data blocks on the first data bus; and

overwriting stored data in a memory space associated with the communications controller with the second plurality of consecutive data blocks.

16. The method of claim 15, wherein transmitting the second plurality of consecutive data blocks comprises transmitting at least one of configuration data associated with the communications controller and application parameters associated with a respective one of the plurality of communications applications.

17. A communication system comprising:

means for controlling transmission and reception of communications data in a network;

means for storing configuration data associated with the means for controlling and for storing application parameters associated with each of a plurality of communications applications; and

means for converting a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read data transfer of the configuration data and the application parameters from the means for storing to the means for controlling and write data transfer of the application parameters from the means for controlling to the means for storing.

18. The system of claim 17, wherein the means for controlling comprises means for initiating the read data transfer as a burst read data transfer and the write data transfer as a burst write data, such that each of the configuration data and the application parameters are configured as a plurality of consecutive data blocks that are sequentially transmitted between the means for controlling and the means for storing.

19. The system of claim 18, wherein the means for controlling comprises means for completing the burst read data transfer and the burst write data transfer based on one of a means for generating an interrupt signal and means for timing the burst read data transfer and the burst write data transfer.

20. The system of claim 19, wherein the means for controlling comprises means for writing a predefined data pattern into an end address register of a plurality of consecutive address registers, and wherein the means for timing comprises means for determining the presence of the predefined data pattern upon completion of a time associated with one of the burst read data transfer and the burst write data transfer.