Interconnect and a Method for Designing an Interconnect

• US 20080307145A1
• Filed: 09/09/2005
• Published: 12/11/2008
• Est. Priority Date: 09/09/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Netanel, Yaron, Goren, Ori
• Granted Patent: US 8,307,147 B2
• Time in Patent Office: Days
• US Class Current: 710/307
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit.

Claims

1. An interconnect comprising:

multiple input ports and multiple output ports;

multiple modular components;

wherein each modular component is adapted to support a certain point-to-point protocol;

wherein at least one modular component comprises a sampling circuit and a bypass circuit, wherein the sampling circuit is selectively bypassed by the bypass circuit.

2. The interconnect according to claim 1 wherein the multiple modular components comprise M expanders, wherein different expanders are coupled to different masters, and wherein each expander is coupled in parallel to S arbiters and multiplexers.

3. The interconnect according to claim 1 wherein the selective bypass is responsive to an expected latency value of the interconnect.

4. The interconnect according to claim 1 wherein the modular components further comprise S splitters, wherein each splitter is adapted to optimize transactions towards a slave associated with the splitter.

5. The interconnect according to claim 1 wherein the modular components further comprise samplers.

6. The interconnect according to claim 1 wherein the modular components further comprise samplers.

7. The interconnect according to claim 1 wherein the modular components further comprise clock separators.

8. The interconnect according to claim 1 wherein the modular components further comprise bus width adaptors.

9. The interconnect according to claim 1 wherein each modular component is selected from a group of modular components that differ from each other by a size of an input bus width of the modular component.

10. The interconnect according to claim 1 wherein a verification environment of a first modular component is a derivative of a verification environment of a second modular component that differs from the first modular component by a input bus width or an output bus width.

11. The interconnect according to claim 1 wherein the modular components are adapted to alter arbitration priority indications of pending transaction requests.

12. A method for designing an interconnect, the method comprises:

determining an amount of input ports, an amount of output ports;

selecting multiple modular components such as to form an interconnect, wherein each modular component is selected from a group of modular components that are verified by parametric verification environment.

13. The method according to claim 12 further comprising determining whether to add a modular sampling component or to bypass at least one sampling circuit within at least one modular component.

14. The method according to claim 12, wherein the determining is responsive to an expected interconnect latency value.

15. The method according to claim 12 wherein the selecting further comprises selecting at least one sampler in response to an expected interconnect latency value.

16. The method according to claim 12 whereas the selecting comprises selecting modular components that are adapted to support a certain point-to-point protocol.

17. The method according to claim 12 wherein the selecting comprises selecting M expanders, whereas different expanders are coupled to different masters, and wherein each expander is coupled in parallel to S arbiters and multiplexers.

18. The method according to claim 12 wherein the selecting comprises selecting S splitters, wherein each splitter is adapted to optimize transactions towards a slave associated with the splitter.

19. The method according to claim 12 wherein the selecting comprises selecting clock separators.

20. The method according to claim 12 wherein the selecting comprises selecting bus width adaptors.