POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE

• US 20080307240A1
• Filed: 06/08/2007
• Published: 12/11/2008
• Est. Priority Date: 06/08/2007
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mair, Hugh, Gammie, Gordon, Ko, Uming, Dahan, Franck, Wang, Alice, Dubost, Gilles, Song, Sang-Won, Wilson, William D.
• Application Number:
  US11/760,263
• Publication Number:
  US 20080307240A1
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).

Claims

1. An electronic circuit comprising:

a power managed circuit; and

a power management control circuit coupled to said power managed circuit and operable to select between at least a first operating performance point and a second higher operating performance point for said power managed circuit, each performance point including a respective pair of voltage and operating frequency, and said power management control circuit further operable to control dynamic power switching of said power managed circuit based on a condition wherein said power managed circuit at a given operating performance point has a static power dissipation, and the dynamic power switching puts the power managed circuit in a lower static power state that dissipates less power than the static power dissipation.

2. The electronic circuit claimed in claim 1 wherein the respective pair of voltage and operating frequency are established at a sufficient spacing that a transition from the second higher operating performance point to the first operating performance point saves as much or more energy in said power managed circuit than activation of dynamic power switching at the second higher operating performance point.

3. An electronic device comprising

a processor;

and

a power management circuit operable to establish a selected operating point including a voltage and operating frequency for said processor thereby defining ranges bounded by adjacent pairs of operating frequencies,

said processor operable to generate a target frequency and operable to determine whether or not the target frequency is outside or within a current range and further operable to configure an operating point transition in said power management circuit when the target frequency is outside the current range.

4. The device claimed in claim 3 wherein said processor is operable to execute a performance prediction process, and wherein the performance prediction process is operable to deliver the target frequency.

5. An electronic circuit comprising:

a processor;

a functional circuit coupled to said processor;

a power management register circuit coupled to said processor for holding configuration bits in said power management register circuit;

a power management control circuit coupled to said power management register circuit and said power management control circuit operable in response to the configuration bits for voltage and frequency scaling combined with conditional dynamic power switching of said processor.

6. The electronic circuit claimed in claim 5 wherein said power management control circuit includes a state machine operable to selectively command a power down of said processor independently of said functional circuit.

7. An electronic circuit comprising:

a processor operable to run an application;

a memory coupled to said processor;

a peripheral including a buffer coupled to said memory and said buffer having a buffer state output; and

a power management control circuit coupled to said processor, to said memory and to said buffer state output, said power management control circuit conditionally operable in a dynamic power switching mode having a controlled sequence wherein said processor runs the application and delivers resulting information to said memory, and power to said processor is substantially lowered, and portions of the resulting information are successively transferred from said memory to said buffer depending on the buffer state output, and then power to said processor is restored.

8. The electronic circuit claimed in claim 7 further comprising a second processor and wherein the controlled sequence includes a data input execution by said second processor and then power to said second processor is substantially lowered generally prior to the first-named processor running the application.

9. An electronic circuit comprising

a power management circuit having a dynamic power switching mode and a sleep control mode;

and

a processor operable in a secure mode and responsive to said power management circuit dynamic power switching mode to perform a context save of the processor before a sleep transition and a context restore on a wakeup transition, said processor further operable to perform a security context save on each exit from secure mode, whereby the security context save does not need to be done on the sleep transition.

10. The electronic circuit claimed in claim 9 wherein said processor has a wakeup transition latency and is operable to perform a security context restore at next entry into secure mode instead of upon the wakeup transition whereby the security context restore is separated from the wakeup transition latency.

11. An electronic circuit comprising:

a power-managed processing circuit operable to execute an application context and said power-managed processing circuit subject to active power consumption when an application is running and static power consumption if its power is on when the application is not running;

a dynamic voltage and frequency scaling (DVFS) circuit operable to establish a voltage and a clock frequency for said power-managed circuit; and

a dynamic power switching (DPS) circuit coupled to said dynamic voltage and frequency scaling circuit, said DPS circuit operable to determine an excess of the clock frequency over a target frequency for said power-managed processing circuit, and when that excess exceeds a predetermined threshold to initiate a context save by said power-managed processing circuit then temporarily substantially reduce the static power consumption.

12. The electronic circuit claimed in claim 11 wherein said power-managed processing circuit is operable to deliver the target frequency to said DPS circuit.

13. An electronic system comprising:

a first integrated circuit including

a processor;

a functional circuit coupled to said processor;

a power management register circuit coupled to said processor to hold configuration bits;

a power management control circuit coupled to said power management register circuit and said power management control circuit operable in response to the configuration bits for combined voltage and frequency scaling and conditional dynamic power switching of said processor; and

a second integrated circuit including

a power controller coupled to said power management control circuit of said first integrated circuit; and

a first controllable voltage power supply responsive to said power controller and said first controllable voltage power supply coupled to supply a controllable voltage to power said processor; and

a second controllable voltage power supply responsive to said power controller and said second controllable voltage power supply coupled to supply a controllable voltage to power said functional circuit said first integrated circuit.

14. The electronic system claimed in claim 13 further comprising a third integrated circuit including a modem coupled to said processor and a second power management control circuit coupled to said first power management control circuit.

15. An electronic camera system comprising:

a camera sensor operable for successive capture operations to capture image frames;

a digital signal processor operable for image processing;

an interconnect coupled to said digital signal processor;

an interconnect clock coupled to said interconnect;

a power management control circuit;

a camera interface coupled to said camera sensor and to said interconnect, said camera interface including a buffer and supporting a smart standby mode wherein when said camera sensor is enabled, a time interval elapses between the successive capture operations, said camera interface operable during the time interval to assert a camera standby signal to the power management control circuit that said camera interface is not accessing said interconnect, said power management control circuit operable during the time interval to shut down said interconnect clock and assert a wait signal to prevent sourcing by said digital signal processor onto said interconnect; and

at substantially the end of the time interval the camera interface further operable to de-assert the camera standby signal to indicate that said camera interface is ready to access said interconnect, and said power management control circuit operable to then disable the wait signal and activate said interconnect clock; and

a display coupled to said digital signal processor.

16. The electronic camera system claimed in claim 15 further comprising a memory controller and wherein said digital signal processor has a memory cache and said display has a display buffer and wherein said power management control circuit is operable to control a frequency scaling circuit coupled to said memory controller and having a latency for changing from one frequency to another frequency, said power management control circuit operable during the latency to pause said camera sensor, and to signal said digital signal processor to operate from said memory cache, and to signal said display to operate from said display buffer independently of said memory controller.

17. A mobile video electronic system comprising:

a processor;

a power management control circuit coupled to said processor and operable for voltage and frequency scaling combined with conditional dynamic power switching of said processor;

a video camera coupled to said processor and to said power management control circuit;

a modem coupled to said power management control circuit; and

a video display operable to display video content and coupled to said power management control circuit.

18. The mobile video electronic system claimed in claim 17 wherein said video display includes a display processor for graphics, video, temporal dithering, plural video image formats, and plural television output types, said display processor coupled to said power management control circuit.

19. A manufacturing process comprising

preparing design code representing a processor and configurable power management circuitry for voltage and clock control by power management control operable for voltage and frequency scaling combined with conditional dynamic power switching of the processor;

and

making at least one integrated circuit by wafer fabrication responsive to said design code.

20. The manufacturing process claimed in claim 19 further comprising verifying operation of the integrated circuit for compliance with a condition for invoking the dynamic power switching.