COMPUTER SYSTEM POWER SOURCE WITH IMPROVED LIGHT-LOAD EFFICIENCY

• US 20080307242A1
• Filed: 10/04/2007
• Published: 12/11/2008
• Est. Priority Date: 06/05/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Qu, Dayu
• Granted Patent: US 8,151,128 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: H02J 9/005 using a power saving mode for copiers G03G15/5004
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: Y02B 70/30 Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y04S 20/20 End-user application control systems

Abstract

Embodiments of the present invention provide a system that supplies power in a computer system. The system includes a power adapter coupled to a source of electrical power and a set of a set of power consumers coupled to a power bus in the computer system. A full-power mechanism coupled between the power adapter and the power bus supplies power for the power consumers while the computer system is operating in a full-power mode. A low-power mechanism coupled between the power adapter and the power bus in parallel with the power mechanism supplies power for the power consumers while the computer system is in operating in a low-power mode.

Claims

1. An apparatus that supplies power in a computer system, comprising:

a power adapter coupled to a source of electrical power;

a set of power consumers coupled to a power bus in the computer system;

a full-power mechanism coupled between the power adapter and the power bus, wherein the full-power mechanism supplies power for the power consumers while the computer system is operating in a full-power mode; and

a low-power mechanism coupled between the power adapter and the power bus in parallel with the power mechanism, wherein the low-power mechanism supplies power for the power consumers while the computer system is in operating in a low-power mode.

2. The apparatus of claim 1, wherein the low-power mechanism is a buck converter, a boost converter, a single-ended primary inductor converter (SEPIC), or another switched-mode power supply.

3. The apparatus of claim 1, wherein the low-power mechanism is a switching element, including a MOSFET transistor, a bipolar junction transistor, a mechanical switch, or another type of switching element.

4. The apparatus of claim 3, further comprising a voltage-reduction mechanism coupled in series with the switching element, wherein the voltage-reduction mechanism reduces the voltage to a level suitable for the power consumers.

5. The apparatus of claim 1, wherein the low-power mechanism is a diode in series with a voltage-reduction mechanism, wherein the voltage-reduction mechanism reduces the voltage to a level suitable for the power consumers.

6. The apparatus of claim 1, further comprising a control mechanism that asserts a control signal to enable the low-power mechanism when the computer system commences operation in low-power mode and to disable the low-power mechanism when the computer system commences operation in full-power mode.

7. The apparatus of claim 6, wherein the control mechanism asserts a second control signal to disable the full-power mechanism when the computer system commences operation in low-power mode and to enable the full-power mechanism when the computer system commences operation in full-power mode.

8. The apparatus of claim 7, wherein the control mechanism temporarily enables both the full-power mechanism and the low-power mechanism as the computer system transitions between the low-power mode and the full-power mode.

9. The apparatus of claim 1, further comprising:

a voltage-sensitive mechanism on the output of the full-power mechanism;

wherein when supplying power for the power consumers, the low-power mechanism outputs a predetermined voltage on the power bus; and

wherein upon detecting the predetermined voltage, the voltage-sensitive mechanism disables the full-power mechanism.

10. A computer system, comprising:

a processor;

a memory coupled to the processor, wherein the memory stores instructions and data for the processor;

a power adapter coupled to a source of electrical power;

a set of power consumers coupled to a power bus in the computer system;

a full-power mechanism coupled between the power adapter and the power bus, wherein the full-power mechanism supplies power for the power consumers while the computer system is operating in a full-power mode; and

a low-power mechanism coupled between the power adapter and the power bus in parallel with the power mechanism, wherein the low-power mechanism supplies power for the power consumers while the computer system is in operating in a low-power mode.

11. The computer system of claim 10, wherein the low-power mechanism is a buck converter, a boost converter, a single-ended primary inductor converter (SEPIC), or another switched-mode power supply.

12. The computer system of claim 10, wherein the low-power mechanism is a switching element, including a MOSFET transistor, a bipolar junction transistor, a mechanical switch, or another type of switching element.

13. The computer system of claim 12, further comprising a voltage-reduction mechanism coupled in series with the switching element, wherein the voltage-reduction mechanism reduces the voltage to a level suitable for the power consumers.

14. The computer system of claim 10, wherein the low-power mechanism is a diode in series with a voltage-reduction mechanism, wherein the voltage-reduction mechanism reduces the voltage to a level suitable for the power consumers.

15. The computer system of claim 10, further comprising a control mechanism that asserts a control signal to enable the low-power mechanism when the computer system commences operation in low-power mode and to disable the low-power mechanism when the computer system commences operation in full-power mode.

16. The computer system of claim 15, wherein the control mechanism asserts a second control signal to disable the full-power mechanism when the computer system commences operation in low-power mode and to enable the full-power mechanism when the computer system commences operation in full-power mode.

17. The computer system of claim 16, wherein the control mechanism temporarily enables both the full-power mechanism and the low-power mechanism as the computer system transitions between the low-power mode and the full-power mode.

18. The computer system of claim 10, further comprising:

a voltage-sensitive mechanism on the output of the full-power mechanism;

wherein when supplying power for the power consumers, the low-power mechanism outputs a predetermined voltage on the power bus; and

wherein upon detecting the predetermined voltage, the voltage-sensitive mechanism disables the full-power mechanism.

19. A circuit for supplying power, comprising:

a full-power mechanism coupled to an input and an output for the circuit, wherein the full-power mechanism is configured to provide power with high power conversion efficiency in a range of full-power output currents;

a low-power mechanism coupled in parallel with the full-power mechanism, wherein the low-power mechanism is configured to provide power with high power conversion efficiency in a range of low-power output currents;

wherein the low-power mechanism is enabled when the circuit is outputting low-power output currents and disabled when the circuit is outputting full-power output currents; and

wherein the full-power mechanism is enabled when the circuit is outputting full-power output currents and disabled when the circuit is outputting low-power output currents.

20. The circuit of claim 19, wherein the full-power mechanism is a buck converter.

21. The circuit of claim 19, wherein the low-power mechanism is a buck converter, a boost converter, a single-ended primary inductor converter (SEPIC), or another switched-mode power supply.

22. The circuit of claim 19, wherein the low-power mechanism is a switching element, including a MOSFET transistor, a bipolar junction transistor, a mechanical switch, or another type of switching element.

23. The circuit of claim 19, wherein both the low-power mechanism and the high-power mechanism are enabled in a range of transition output currents between the range of low-power output currents and the range of full-power output currents.

24. The circuit of claim 19, further comprising:

a voltage-sensitive mechanism on the output of the full-power mechanism;

wherein when providing power, the low-power mechanism outputs a predetermined voltage; and

wherein upon detecting the predetermined voltage, the voltage-sensitive mechanism disables the full-power mechanism.

25. A method for supplying power in a computer system that supports operating in a full-power mode and a low-power mode, comprising:

operating in full-power mode, wherein operating in the full-power mode involves disabling a low-power mechanism and supplying power to a set of power consumers coupled to a power bus in the computer system using a full-power mechanism; and

upon commencing operation in low-power mode, disabling the full-power mechanism and supplying power to the set of power consumers using the low-power mechanism.